专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09590797B1 Edge rate control calibration 有权
标题翻译：边缘率控制校准
公开(公告)号：US09590797B1
公开(公告)日：2017-03-07
申请号：US15143282
申请日：2016-04-29
申请人： Cavium, Inc.
发明人： Jonathan K. Brown , Ethan Crain
IPC分类号： H03D3/24 , H04L7/00 , H04L7/033
CPC分类号： H04L7/0025 , H03K3/0315 , H03K5/135 , H04L7/0337
摘要： In an example embodiment, a circuit includes an oscillator providing a set of clock phase signals. A main edge rate controller (ERC) coupled to the oscillator is configured to adjust an edge rate of each clock phase signal of the set of clock phase signals. An interpolator coupled to the main ERC is configured to interpolate the adjusted set of clock phase signals to provide at least one desired phase output signal. An edge rate controller calibrator comprises a ring oscillator including at least three ERCs connected in a loop, a counter configured to count a number of cycles of the ring oscillator over a given period, and a finite state machine (FSM) configured to compare the counter count to a given value corresponding to an operating frequency of the circuit and to adjust operation of the circuit based on the comparison.
摘要翻译：在示例实施例中，电路包括提供一组时钟相位信号的振荡器。耦合到振荡器的主边沿速率控制器（ERC）被配置为调整该组时钟相位信号的每个时钟相位信号的边沿速率。耦合到主ERC的内插器被配置为内插经调整的时钟相位信号组，以提供至少一个期望的相位输出信号。边缘速率控制器校准器包括环形振荡器，其包括以循环连接的至少三个ERC，配置成在给定周期内对环形振荡器的周期数进行计数的计数器和被配置为比较计数器的有限状态机（FSM）计数到与电路的工作频率相对应的给定值，并且基于该比较来调整电路的操作。

2. 发明授权

US09904305B2 Voltage regulator with adaptive bias network 有权
公开(公告)号：US09904305B2
公开(公告)日：2018-02-27
申请号：US15143302
申请日：2016-04-29
申请人： Cavium, Inc.
发明人： Jonathan K. Brown , JingDong Deng
IPC分类号： G05F1/575 , G05F1/46
CPC分类号： G05F1/575 , G05F1/462 , G05F1/467 , G05F1/468
摘要： A low drop-out voltage regulator includes an error amplifier that generates an amplified error voltage, the error amplifier including a first input for receiving a reference voltage, a second input for receiving a feedback voltage, a bias terminal for receiving an adaptive bias current, and an output. A pass gate providing an output voltage includes a first input connected to a supply voltage and a second input connected to the error amplifier output. A feedback network generating the feedback voltage includes a first terminal connected to the output of the pass gate and a second terminal connected to the second input of the error amplifier. An adaptive bias network providing the adaptive bias current includes a first transistor connected to the bias terminal of the error amplifier, a second transistor connected to the first transistor as a current mirror, and a third transistor connected in parallel with the pass gate.

3. 发明申请

US20170315574A1 VOLTAGE REGULATOR WITH ADAPTIVE BIAS NETWORK 有权
公开(公告)号：US20170315574A1
公开(公告)日：2017-11-02
申请号：US15143302
申请日：2016-04-29
申请人： Cavium, Inc.
发明人： Jonathan K. Brown , JingDong Deng
IPC分类号： G05F1/575 , G05F1/46 , G05F1/59
CPC分类号： G05F1/575 , G05F1/462 , G05F1/467 , G05F1/468
摘要： A low drop-out voltage regulator includes an error amplifier that generates an amplified error voltage, the error amplifier including a first input for receiving a reference voltage, a second input for receiving a feedback voltage, a bias terminal for receiving an adaptive bias current, and an output. A pass gate providing an output voltage includes a first input connected to a supply voltage and a second input connected to the error amplifier output. A feedback network generating the feedback voltage includes a first terminal connected to the output of the pass gate and a second terminal connected to the second input of the error amplifier. An adaptive bias network providing the adaptive bias current includes a first transistor connected to the bias terminal of the error amplifier, a second transistor connected to the first transistor as a current mirror, and a third transistor connected in parallel with the pass gate.

4. 发明授权

US09470719B2 Testing semiconductor devices 有权
标题翻译：测试半导体器件
公开(公告)号：US09470719B2
公开(公告)日：2016-10-18
申请号：US14541977
申请日：2014-11-14
申请人： Cavium, Inc.
发明人： Scott E. Meninger , Jonathan K. Brown , Rohan Arora
IPC分类号： G01R31/28 , G01R1/20 , G01R31/02 , G01R31/26
CPC分类号： G01R1/20 , G01R1/07385 , G01R31/025 , G01R31/2601
摘要： An apparatus includes a plurality of semiconductor devices and an electrical input device for applying voltage to the plurality of semiconductor devices. There is a switching array configured to sequentially interconnect the electrical input device to each of the semiconductor devices and disconnect the other semiconductor devices from the electrical input device. The semiconductor device connected to the electrical input device is a device under test that produces a test current and the other semiconductor devices are devices not under test that produce, in the aggregate, a leakage current. There is an output node interconnected to the switching array for enabling the measurement of the test current at the output node. There is also a leakage current compensator connected to the output node and the switching array that is configured to divert the leakage current away from the output node.
摘要翻译：一种装置包括多个半导体器件和用于向多个半导体器件施加电压的电输入器件。存在配置成将电输入设备顺序地互连到每个半导体器件并将其它半导体器件与电输入器件断开的开关阵列。连接到电输入装置的半导体器件是被测试的器件，其产生测试电流，并且其它半导体器件是未经测试的集合地产生泄漏电流的器件。存在与开关阵列互连的输出节点，用于测量输出节点上的测试电流。还有一个泄漏电流补偿器连接到输出节点和开关阵列，其被配置为将泄漏电流转移离开输出节点。

5. 发明申请

US20160139180A1 TESTING SEMICONDUCTOR DEVICES 有权
标题翻译：测试半导体器件
公开(公告)号：US20160139180A1
公开(公告)日：2016-05-19
申请号：US14541977
申请日：2014-11-14
申请人： Cavium, Inc.
发明人： Scott E. Meninger , Jonathan K. Brown , Rohan Arora
IPC分类号： G01R1/20 , G01R31/26 , G01R31/02
CPC分类号： G01R1/20 , G01R1/07385 , G01R31/025 , G01R31/2601
摘要： An apparatus includes a plurality of semiconductor devices and an electrical input device for applying voltage to the plurality of semiconductor devices. There is a switching array configured to sequentially interconnect the electrical input device to each of the semiconductor devices and disconnect the other semiconductor devices from the electrical input device. The semiconductor device connected to the electrical input device is a device under test that produces a test current and the other semiconductor devices are devices not under test that produce, in the aggregate, a leakage current. There is an output node interconnected to the switching array for enabling the measurement of the test current at the output node. There is also a leakage current compensator connected to the output node and the switching array that is configured to divert the leakage current away from the output node.
摘要翻译：一种装置包括多个半导体器件和用于向多个半导体器件施加电压的电输入器件。存在配置成将电输入设备顺序地互连到每个半导体器件并将其它半导体器件与电输入器件断开的开关阵列。连接到电输入装置的半导体器件是被测试的器件，其产生测试电流，并且其它半导体器件是未经测试的集合地产生泄漏电流的器件。存在与开关阵列互连的输出节点，用于测量输出节点上的测试电流。还有一个泄漏电流补偿器连接到输出节点和开关阵列，其被配置为将泄漏电流转移离开输出节点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式