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    • 1. 发明授权
    • Reset and resettable circuits
    • 复位和复位电路
    • US08514014B2
    • 2013-08-20
    • US13023751
    • 2011-02-09
    • Cathal MurphyMichael ColnGary CarreauAlain Valentin GueryBruce Amazeen
    • Cathal MurphyMichael ColnGary CarreauAlain Valentin GueryBruce Amazeen
    • H03F1/02
    • H03F1/34H03F3/45475H03F3/68H03F2203/45514
    • An amplifier system can include a feedback amplifier circuit having an amplifier, a feedback capacitor connected between an input terminal and an output terminal of the amplifier by at least one first switch, and a reset capacitor connected across the feedback capacitor by at least one second switch and between a pair of reference voltages by at least one third switch. During an input-signal processing phase of operation, a control circuit may close the at least one first switch and open the at least one second switch to electrically connect the feedback capacitor between the input and output terminals to engage feedback processing by the feedback amplifier circuit, and close the third switch to electrically connect the reset capacitor between the first and second voltages to charge the reset capacitor to a selectable voltage difference. During a reset phase of operation, the control circuit may open the at least one third switch, close the at least one second switch and open the at least one first switch to electrically connect the reset capacitor across the feedback capacitor to reset the feedback capacitor using the reset capacitor. The amplifier system can optionally include a plurality of the feedback amplifier circuits.
    • 放大器系统可以包括具有放大器的反馈放大器电路,通过至少一个第一开关连接在放大器的输入端子和输出端子之间的反馈电容器以及通过至少一个第二开关连接在反馈电容器上的复位电容器 以及通过至少一个第三开关在一对参考电压之间。 在操作的输入信号处理阶段期间,控制电路可以关闭所述至少一个第一开关并且打开所述至少一个第二开关以将所述反馈电容器电连接在所述输入和输出端子之间,以接收所述反馈放大器电路的反馈处理 并且关闭第三开关以在第一和第二电压之间电连接复位电容器,以将复位电容器充电至可选择的电压差。 在复位操作阶段期间,控制电路可以打开至少一个第三开关,闭合至少一个第二开关并且打开至少一个第一开关,以使反复电容器上的复位电容器电连接以使反馈电容器复位,以使用 复位电容。 放大器系统可以可选地包括多个反馈放大器电路。
    • 3. 发明授权
    • Self-timed clocked analog to digital converter
    • 自定时钟模数转换器
    • US07834793B2
    • 2010-11-16
    • US12324121
    • 2008-11-26
    • Gary CarreauBruce Amazeen
    • Gary CarreauBruce Amazeen
    • H03M1/12
    • H03M1/462
    • An SAR analog-to-digital converter performs bit decisions in each of a plurality of clock cycles. A sense circuit monitors signals input to a latch within a comparator of the ADC and, when the signals are sufficient to establish a bit decision, the sense circuit terminates a currently active clock cycle causes a bit decision to occur in advance of a normal expiration of the clock cycle. If the signals are insufficient to establish a bit decision prior to a default expiration time of the clock cycle, the clock cycle concludes at the default expiration time.
    • SAR模数转换器在多个时钟周期中的每一个中执行位决定。 感测电路监视输入到ADC的比较器内的锁存器的信号,并且当信号足以建立位决定时,感测电路终止当前活动的时钟周期,导致在正常到期之前发生位决定 时钟周期。 如果信号不足以在时钟周期的默认到期时间之前建立位决定,则时钟周期以默认的到期时间结束。