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1. 发明授权

US09165968B2 3D-stacked backside illuminated image sensor and method of making the same 有权
标题翻译： 3D叠层背面照明图像传感器及其制作方法
公开(公告)号：US09165968B2
公开(公告)日：2015-10-20
申请号：US13616850
申请日：2012-09-14
申请人： Calvin Yi-Ping Chao , Kuo-Yu Chou , Fu-Lung Hsueh
发明人： Calvin Yi-Ping Chao , Kuo-Yu Chou , Fu-Lung Hsueh
IPC分类号： H01L27/146 , H04N5/374
CPC分类号： H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/14641 , H04N5/374
摘要： A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.
摘要翻译：提供一种堆叠式图像传感器及其制造方法。堆叠图像传感器包括其上具有像素阵列的上部芯片。第二芯片包括与像素阵列的列和行相关联的多个列电路和行电路，并且被布置在多个组中的各个列电路和行电路区域中。在每个芯片上形成芯片间接合焊盘。在一个实施例中，第二芯片上的芯片间接合焊盘被线性布置并且被包含在列电路区域和行电路区域内。在其他实施例中，芯片间接合焊盘相对于彼此交错。在一些实施例中，像素阵列的行和列包括多个信号线，并且相应的列电路区域和行电路区域还包括多个芯片间接合焊盘。

2. 发明授权

US08762897B2 Semiconductor device design system and method of using the same 有权
标题翻译：半导体器件设计系统及其使用方法
公开(公告)号：US08762897B2
公开(公告)日：2014-06-24
申请号：US13475853
申请日：2012-05-18
申请人： Chih-Hsien Chang , Yung-Chow Peng , Fu-Lung Hsueh
发明人： Chih-Hsien Chang , Yung-Chow Peng , Fu-Lung Hsueh
IPC分类号： G06F17/50 , G03F1/00 , G21K5/00 , G06F19/00
CPC分类号： G06F17/5081 , G03F1/00 , G06F17/5009 , G06F17/5045 , G06F17/5068 , G06F19/00 , G06F2217/12 , G21K5/00
摘要： A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.
摘要翻译：电路设计系统包括被配置为产生电路的示意图信息和预着色信息的示意性设计工具。电路设计系统还包括被配置为在非暂时计算机可读介质上存储原理图信息和预着色信息的网表文件，以及被配置为从网表文件中提取预着色信息的提取工具。包括在电路设计系统中的布局设计工具被配置为基于原理图信息和预着色信息设计至少一个掩模。电路设计系统还包括布局与示意性比较工具，其被配置为将至少一个掩模与示意图信息和预着色信息进行比较。

3. 发明授权

US08698566B2 Phase locked loop calibration 有权
标题翻译：锁相环校准
公开(公告)号：US08698566B2
公开(公告)日：2014-04-15
申请号：US13252498
申请日：2011-10-04
申请人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Fu-Lung Hsueh , Yuwen Swei
发明人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Fu-Lung Hsueh , Yuwen Swei
IPC分类号： H03L7/085 , H03L7/10 , H03B5/12
CPC分类号： H03L7/102 , H03L7/099 , H03L2207/06
摘要： An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.
摘要翻译：电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。校准电路包括两个比较器，并向LCVCO提供粗调信号。两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。粗调频率范围大于微调频率范围。

4. 发明授权

US08432204B1 Current-controlled oscillator (CCO) based PLL 有权
标题翻译：基于电流控制振荡器（CCO）的PLL
公开(公告)号：US08432204B1
公开(公告)日：2013-04-30
申请号：US13344637
申请日：2012-01-06
申请人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Yuwen Swei , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Yuwen Swei , Fu-Lung Hsueh
IPC分类号： H03L7/06
CPC分类号： H03L7/102 , H03L7/099 , H03L7/104
摘要： A PLL circuit includes a phase frequency detector; a programmable charge pump coupled to an output of the phase frequency detector; a loop filter coupled to an output of the charge pump, the loop filter providing a fine tuning voltage; a first voltage-to-current converter, the first voltage-to-current converter providing a fine tuning current corresponding to the fine tuning voltage; a current-controlled oscillator (CCO); a feedback divider coupled to an output of the CCO and an input of the phase frequency detector; and an analog calibration circuit. The analog calibration circuit provides a coarse adjustment current for coarse adjustments to a frequency pivot point for an oscillator frequency of the CCO, wherein the CCO generates a frequency signal at an output responsive to a summed coarse adjustment and fine tuning current, wherein the frequency pivot point is continuously adjustable.
摘要翻译： PLL电路包括相位检波器; 耦合到所述相位频率检测器的输出的可编程电荷泵; 耦合到电荷泵的输出的环路滤波器，所述环路滤波器提供微调电压; 第一电压 - 电流转换器，第一电压 - 电流转换器提供对应于微调电压的微调电流; 电流控制振荡器（CCO）; 耦合到CCO的输出的反馈分压器和相位频率检测器的输入端; 和模拟校准电路。模拟校准电路提供用于对CCO的振荡器频率的频率枢转点进行粗调整的粗调电流，其中CCO响应于总和的粗调和微调电流而在输出端产生频率信号，其中频率枢轴点连续可调。

5. 发明授权

US08427240B2 Low-noise amplifier with gain enhancement 有权
标题翻译：具有增益增益的低噪声放大器
公开(公告)号：US08427240B2
公开(公告)日：2013-04-23
申请号：US12968342
申请日：2010-12-15
申请人： Hsieh-Hung Hsieh , Po-Yi Wu , Ho-Hsiang Chen , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Hsieh-Hung Hsieh , Po-Yi Wu , Ho-Hsiang Chen , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H03F3/04
CPC分类号： H03G1/0029 , H03F1/223 , H03F3/195 , H03F2200/249 , H03F2200/318 , H03F2200/408 , H03F2200/411 , H03F2200/451 , H03F2200/492
摘要： A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element.
摘要翻译：低噪声放大器（“LNA”）包括第一共源共栅增益级，其包括被配置为接收射频（“RF”）输入信号的第一互补金属氧化物半导体（“CMOS”）晶体管和耦合到输出节点。第一感应栅极网络耦合到第二CMOS晶体管的栅极，用于增加第一共源共栅增益级的增益。第一感应栅极网络具有非零电感输入阻抗并且包括至少一个无源电路元件。

6. 发明申请

US20120286888A1 Switched Capacitor Array for Voltage Controlled Oscillator 审中-公开
标题翻译：用于压控振荡器的开关电容阵列
公开(公告)号：US20120286888A1
公开(公告)日：2012-11-15
申请号：US13103592
申请日：2011-05-09
申请人： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H03B5/12 , H03H11/00
CPC分类号： H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2201/0266
摘要： A system comprises a voltage controlled oscillator comprising an inductor and a variable capacitor and a switched capacitor array connected in parallel with the variable capacitor. The switched capacitor array further comprises a plurality of capacitor banks wherein a thermometer code is employed to control each capacitor bank. In addition, the switched capacitor array provides N tuning steps for the oscillation frequency of the voltage controlled oscillator when the switched capacitor array is controlled by an n-bit thermometer code.
摘要翻译：一种系统包括压控振荡器，其包括电感器和可变电容器以及与可变电容器并联连接的开关电容器阵列。开关电容器阵列还包括多个电容器组，其中使用温度计代码来控制每个电容器组。此外，当开关电容器阵列由n位温度计代码控制时，开关电容器阵列为压控振荡器的振荡频率提供N个调谐步骤。

7. 发明授权

US08258879B2 Capacitor coupled quadrature voltage controlled oscillator 有权
标题翻译：电容耦合正交压控振荡器
公开(公告)号：US08258879B2
公开(公告)日：2012-09-04
申请号：US12907294
申请日：2010-10-19
申请人： Ying-Ta Lu , Ho-Hsiang Chen , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Ying-Ta Lu , Ho-Hsiang Chen , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H03L7/00
CPC分类号： H03B27/00 , H03B5/1215 , H03B5/1228
摘要： A quadrature oscillator includes a first oscillator having a first second-order harmonic node, a second oscillator having a second second-order harmonic node, and at least one capacitor coupling the first second-order harmonic node and the second second-order harmonic node. The first oscillator is configured to supply an in-phase signal and the second oscillator is configured to supply a quadrature signal.
摘要翻译：正交振荡器包括具有第一二次谐波节点的第一振荡器，具有第二二次谐波节点的第二振荡器和耦合第一二次谐波节点和第二二次谐波节点的至少一个电容器。第一振荡器被配置为提供同相信号，并且第二振荡器被配置为提供正交信号。

8. 发明授权

US08258602B2 Bipolar junction transistors having a fin 有权
标题翻译：具有翅片的双极结晶体管
公开(公告)号：US08258602B2
公开(公告)日：2012-09-04
申请号：US12618425
申请日：2009-11-13
申请人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
发明人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/73 , H01L21/823431
摘要： Design and methods for fabricating bipolar junction transistors are described. In one embodiment, a semiconductor device includes a first fin comprising a first emitter region, a first base region, and a first collector region. The first emitter region, the first base region, and the first collector region form a bipolar junction transistor. A second fin is disposed adjacent and parallel to the first fin. The second fin includes a first contact to the first base region.
摘要翻译：描述用于制造双极结型晶体管的设计和方法。在一个实施例中，半导体器件包括包括第一发射极区域，第一基极区域和第一集电极区域的第一鳍片。第一发射极区域，第一基极区域和第一集电极区域形成双极结型晶体管。第二翅片邻近并平行于第一翅片设置。第二鳍片包括与第一基底区域的第一接触。

9. 发明授权

US08183910B2 Circuit and method for a digital process monitor 有权
标题翻译：数字过程监控的电路和方法
公开(公告)号：US08183910B2
公开(公告)日：2012-05-22
申请号：US12495024
申请日：2009-06-30
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L35/00 , H01L37/00 , H03K3/42 , H03K17/78
CPC分类号： G01R31/3004 , G01R31/31703
摘要： A circuit and method for a digital process monitor is disclosed. Circuits for comparing a current or voltage to a current or voltage corresponding to a device having process dependent circuit characteristics are disclosed, having converters for converting current or voltage measurements proportional to the process dependent circuit characteristic to a digital signal and outputting the digital signal for monitoring. The process dependent circuit characteristics may be selected from transistor threshold voltage, transistor saturation current, and temperature dependent quantities. Calibration is performed using digital techniques such as digital filtering and digital signal processing. The digital process monitor circuit may be formed as a scribe line circuit for wafer characterization or placed in an integrated circuit die as a macro. The process monitor circuit may be accessed using probe pads or scan test circuitry. Methods for monitoring process dependent characteristics using digital outputs are disclosed.
摘要翻译：公开了一种用于数字处理监视器的电路和方法。公开了用于将电流或电压与对应于具有过程相关电路特性的器件相对应的电流或电压进行比较的电路，具有用于将与过程相关的电路特性成比例的电流或电压测量值转换为数字信号的转换器，并输出用于监测的数字信号。处理相关电路特性可以选自晶体管阈值电压，晶体管饱和电流和温度依赖量。使用数字滤波和数字信号处理等数字技术进行校准。数字处理监视电路可以形成为用于晶片表征的划线电路或者作为宏放置在集成电路管芯中。可以使用探针焊盘或扫描测试电路来访问过程监控电路。公开了使用数字输出来监视与过程有关的特性的方法。

10. 发明申请

US20110265051A1 Method for Substrate Noise Analysis 有权
标题翻译：基板噪声分析方法
公开(公告)号：US20110265051A1
公开(公告)日：2011-10-27
申请号：US12766732
申请日：2010-04-23
申请人： Tzu-Jin Yeh , Kal-Wen Tan , Chewn-Pu Jou , Sally Liu , Fu-Lung Hsueh
发明人： Tzu-Jin Yeh , Kal-Wen Tan , Chewn-Pu Jou , Sally Liu , Fu-Lung Hsueh
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal.
摘要翻译：根据实施例，用于衬底噪声分析的方法包括使用基于第一处理器的系统，创建和模拟包括晶体管的多端子模型的电路原理图，然后基于电路原理图中所示的特性创建布局和仿真结果的模拟。多端子模型包括源极端子，栅极端子，漏极端子，主体端子和保护环端子。

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