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    • 2. 发明授权
    • Monitoring structure and monitoring method for silicon wet etching depth
    • 硅湿蚀刻深度监测结构及监测方法
    • US09006867B2
    • 2015-04-14
    • US14364933
    • 2012-11-20
    • CSMC Technologies FAB1 Co., Ltd.
    • Xinwei ZhangChangfeng XiaChengjian FanWei Su
    • H01L21/66H01L21/306H01L21/308
    • H01L22/30H01L21/30608H01L21/3083H01L22/12
    • A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are Wu and W1 respectively, Wu=du/0.71, and W1=du/0.71, where du is the maximum wet etching depth to be monitored, and d1 is the minimum of the wet etching depth to be monitored. The method includes: performing anisotropic wet etching on a monocrystalline silicon wafer according to a pattern with a monitoring pattern, forming an etched groove to be monitored and a structure for monitoring the depth of the groove, and then monitoring the structure to monitor the wet etching depth. The etching depth of the groove can be monitored with low costs, and a higher monitoring accuracy is obtained.
    • 提供了硅湿蚀刻​​深度的监测结构和相关监测方法。 该结构包括形成在单晶硅材料上的湿蚀刻槽,其至少两个顶表面是矩形; 并且槽的顶面宽度分别为Wu和W1,Wu = du / 0.71,W1 = du / 0.71,其中du是要监测的最大湿蚀刻深度,d1是湿蚀刻深度的最小值 被监视。 该方法包括:根据具有监测图案的图案在单晶硅晶片上进行各向异性湿蚀刻,形成待监测的蚀刻凹槽和用于监测凹槽深度的结构,然后监测结构以监测湿蚀刻 深度。 可以以低成本监测凹槽的蚀刻深度,并且获得更高的监视精度。
    • 3. 发明申请
    • MONITORING STRUCTURE AND MONITORING METHOD FOR SILICON WET ETCHING DEPTH
    • 监测硅蚀刻深度的结构和监测方法
    • US20140346647A1
    • 2014-11-27
    • US14364933
    • 2012-11-20
    • CSMC TECHNOLOGIES FAB1 CO.,LTD
    • Xinwei ZhangChangfeng XiaChengjian FanWei Su
    • H01L21/66H01L21/308
    • H01L22/30H01L21/30608H01L21/3083H01L22/12
    • A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are Wu and Wl respectively, Wu=du/0.71, and Wl=du/0.71, where du is the maximum wet etching depth to be monitored, and dl is the minimum of the wet etching depth to be monitored. The method includes: performing anisotropic wet etching on a monocrystalline silicon wafer according to a pattern with a monitoring pattern, forming an etched groove to be monitored and a structure for monitoring the depth of the groove, and then monitoring the structure to monitor the wet etching depth. The etching depth of the groove can be monitored with low costs, and a higher monitoring accuracy is obtained.
    • 提供了硅湿蚀刻​​深度的监测结构和相关监测方法。 该结构包括形成在单晶硅材料上的湿蚀刻槽,其至少两个顶表面是矩形; 并且槽的顶面宽度分别为Wu和Wl,Wu = du / 0.71,Wl = du / 0.71,其中du是要监测的最大湿蚀刻深度,d1是湿蚀刻深度的最小值 被监视。 该方法包括:根据具有监测图案的图案在单晶硅晶片上进行各向异性湿蚀刻,形成待监测的蚀刻凹槽和用于监测凹槽深度的结构,然后监测结构以监测湿蚀刻 深度。 可以以低成本监测凹槽的蚀刻深度,并且获得更高的监视精度。
    • 4. 发明申请
    • PARALLEL PLATE CAPACITOR AND ACCELERATION SENSOR COMPRISING SAME
    • 平行平板电容器和加速传感器包括相同
    • US20150233965A1
    • 2015-08-20
    • US14435925
    • 2013-08-30
    • CSMC TECHNOLOGIES FAB1 CO., LTD.
    • Meihan GuoXinwei ZhangChangfeng XiaWei Su
    • G01P15/125B81B7/02H02N1/08
    • G01P15/125B81B7/02G01P2015/0837H01G5/16H02N1/08
    • A parallel plate capacitor includes a first polar plate (10), and a second polar plate disposed opposite to the first polar plate (10). The parallel plate capacitor further includes at least a pair of sensitive units disposed on a substrate forming the first polar plate (10); the sensitive units includes sensitive elements (21a, 21b, 22a, 22b) and element connecting arms (23a, 23b, 24a, 24b) connecting the sensitive elements (21a, 21b, 22a, 22b) to the first polar plate (10). The parallel plate capacitor further includes anchoring bases (30, 31, 32, 33) disposed on a substrate where the second polar plate is located; the anchoring bases (30, 31, 32, 33) are connected to the element connecting arms (23a, 23b, 24a, 24b) via cantilever beams (30a, 30b, 31a, 31b, 32a, 32b, 33a, 33b); each element connecting arm (23a, 23b, 24a, 24b) is connected to at least two anchoring bases (30, 31, 32, 33), which are symmetric with respect to the element connecting arm. The parallel plate capacitor is more likely to be influenced by an external factor, thus being more likely to experience capacitance change. An acceleration sensor including the parallel plate capacitor is also provided.
    • 平行板电容器包括第一极板(10)和与第一极板(10)相对设置的第二极板。 平行板电容器还包括至少一对设置在形成第一极板(10)的基板上的敏感单元。 敏感单元包括将敏感元件(21a,21b,22a,22b)连接到第一极板(10)的敏感元件(21a,21b,22a,22b)和元件连接臂(23a,23b,24a,24b)。 平行板电容器还包括设置在第二极板所在的基板上的固定基座(30,31,32,33)。 通过悬臂梁(30a,30b,31a,31b,32a,32b,33a,33b)将锚定基座(30,31,32,33)连接到元件连接臂(23a,23b,24a,24b) 每个元件连接臂(23a,23b,24a,24b)连接到至少两个相对于元件连接臂对称的锚定基座(30,31,32,33)。 并联平板电容更可能受到外部因素的影响,因此更容易发生电容变化。 还提供了包括平行板电容器的加速度传感器。