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1. 发明授权

US09836391B2 System and method of page buffer operation for memory devices 有权
公开(公告)号：US09836391B2
公开(公告)日：2017-12-05
申请号：US14457567
申请日：2014-08-12
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Hong Beom Pyeon , Jin-Ki Kim , HakJune Oh
IPC分类号： G06F12/02 , G06F12/0893 , G11C7/10
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/1044 , G06F2212/2022 , G06F2212/3042 , G06F2212/7203 , G06F2212/7208 , G11C7/1039 , G11C7/106 , G11C7/1087 , G11C2207/2245
摘要： Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

2. 发明授权

US09281047B2 Dynamic random access memory with fully independent partial array refresh function 有权
公开(公告)号：US09281047B2
公开(公告)日：2016-03-08
申请号：US14265852
申请日：2014-04-30
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Jin-Ki Kim , HakJune Oh
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/40622
摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

3. 发明授权

US10224098B2 Non-volatile memory device 有权
公开(公告)号：US10224098B2
公开(公告)日：2019-03-05
申请号：US15937937
申请日：2018-03-28
申请人： Conversant Intellectual Property Management Inc.
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C7/00 , G11C11/56 , G11C7/10 , G11C16/10 , G11C16/26 , G06F1/12 , G11C16/16 , G11C16/34 , G11C16/06
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

4. 发明授权

US09196319B2 Pre-charge voltage generation and power saving modes 有权
标题翻译：预充电电压和省电模式
公开(公告)号：US09196319B2
公开(公告)日：2015-11-24
申请号：US14216024
申请日：2014-03-17
申请人： Conversant Intellectual Property Management Inc.
发明人： Valerie Lines , HakJune Oh
IPC分类号： G11C5/14 , G11C7/10 , G11C8/08
CPC分类号： G11C5/148 , G11C5/147 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C2207/2227
摘要： A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.
摘要翻译：系统包括电压发生器，以产生用于对存储器电路中的一个或多个信号进行预充电的预充电电压信号。一个或多个信号可以是用于访问存储器的数据总线。电压发生器可以包括指示存储器电路是否被设置为省电模式的输入。根据一个实施例，输入调节由电压发生器产生的预充电电压信号的幅度。这种实施例对于常规方法是有用的，因为调节预充电电压可导致功率节省。例如，在省电模式下，电压发生器电路可以将预充电电压调整为减小与预充电电压相关联的漏电流量的值。减少相对于预充电电压的泄漏意味着所节省的功率可以用于其他有用的目的。

5. 发明授权

US09779804B2 Flash memory system 有权
公开(公告)号：US09779804B2
公开(公告)日：2017-10-03
申请号：US15345552
申请日：2016-11-08
申请人： Conversant Intellectual Property Management Inc.
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C7/00 , G11C11/56 , G11C7/10 , G11C16/10 , G11C16/26 , G06F1/12 , G11C16/16 , G11C16/34 , G11C16/06
CPC分类号： G11C11/5628 , G06F1/12 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C2207/107
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

6. 发明授权

US11017849B2 Non-volatile memory device with concurrent bank operations 有权
公开(公告)号：US11017849B2
公开(公告)日：2021-05-25
申请号：US16866818
申请日：2020-05-05
申请人： Conversant Intellectual Property Management Inc.
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C11/56 , G11C7/10 , G11C16/10 , G11C16/26 , G11C16/16 , G11C16/34 , G06F1/12 , G11C16/06
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

7. 发明授权

US09972381B1 Memory with output control 有权
公开(公告)号：US09972381B1
公开(公告)日：2018-05-15
申请号：US15868219
申请日：2018-01-11
申请人： Conversant Intellectual Property Management Inc.
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C7/00 , G11C11/56 , G11C16/26 , G11C7/10 , G11C16/10 , G06F1/12 , G11C16/16 , G11C16/34 , G11C16/06
CPC分类号： G11C11/5628 , G06F1/12 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C2207/107
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

8. 发明授权

US10679695B2 Non-volatile memory device 有权
公开(公告)号：US10679695B2
公开(公告)日：2020-06-09
申请号：US16249482
申请日：2019-01-16
申请人： Conversant Intellectual Property Management Inc.
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C7/00 , G11C11/56 , G11C7/10 , G11C16/34 , G11C16/10 , G11C16/26 , G06F1/12 , G11C16/16 , G11C16/06
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

9. 发明授权

US09966133B2 Flash memory device 有权
公开(公告)号：US09966133B2
公开(公告)日：2018-05-08
申请号：US15692206
申请日：2017-08-31
申请人： Conversant Intellectual Property Management Inc.
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C7/00 , G11C11/56 , G11C16/34 , G11C16/16 , G06F1/12 , G11C7/10 , G11C16/10 , G11C16/26 , G11C16/06
CPC分类号： G11C11/5628 , G06F1/12 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C2207/107
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

10. 发明授权

US09767881B2 Dynamic random access memory with fully independent partial array refresh function 有权
公开(公告)号：US09767881B2
公开(公告)日：2017-09-19
申请号：US15054873
申请日：2016-02-26
申请人： Conversant Intellectual Property Management Inc.
发明人： Jin-Ki Kim , HakJune Oh
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/40622
摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

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