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1. 发明申请

US20100171645A1 N-BIT ADC READER 有权
标题翻译： N-Bit ADC读取器
公开(公告)号：US20100171645A1
公开(公告)日：2010-07-08
申请号：US12631998
申请日：2009-12-07
申请人： CHUN CHEUNG , WEIHONG QIU , ROBERT H. ISHAM , MIR MAHIN
发明人： CHUN CHEUNG , WEIHONG QIU , ROBERT H. ISHAM , MIR MAHIN
IPC分类号： H03M1/12
CPC分类号： H03M1/20 , G01R27/14
摘要： An integrated circuit including a single input pin for determining a value associated with a resistor divider. The circuit includes first circuitry for determining a resistor ratio of the resistor divider through the single input pin. A first register stores a first group of bits representing the resistor ratio. The first group of bits comprises the least significant bits of the value. Second circuitry determines an equivalent resistance of the resistor divider through the single input pin. A second register stores a second group of bits representing the equivalent resistance. The second group of bits comprises the most significant bits of the value associated with the resistor divider.
摘要翻译：包括用于确定与电阻分压器相关联的值的单个输入引脚的集成电路。该电路包括用于通过单个输入引脚确定电阻分压器的电阻比的第一电路。第一寄存器存储表示电阻器比率的第一组位。第一组比特包括该值的最低有效位。第二个电路通过单个输入引脚确定电阻分压器的等效电阻。第二寄存器存储表示等效电阻的第二组位。第二组位包括与电阻分压器相关联的值的最高有效位。

2. 发明申请

US20080238197A1 MULTI-MODULE CURRENT SHARING SCHEME 有权
标题翻译：多模块电流共享方案
公开(公告)号：US20080238197A1
公开(公告)日：2008-10-02
申请号：US11775306
申请日：2007-07-10
申请人： CHUN CHEUNG , STAN WIETECHA
发明人： CHUN CHEUNG , STAN WIETECHA
IPC分类号： H02J3/00
CPC分类号： H02J1/14 , Y10T307/414
摘要： A circuit provides multi-module current sharing for circuit modules. The circuit includes an error amplifier having a negative and a positive input and an output. The positive input of the error amplifier is connected to a reference voltage. A buffered differential amplifier has an output connected to the negative input of the error amplifier and a positive and a negative input. A correction current is sourced to the negative input of the buffered differential amplifier. A resistor connected to the negative input of the buffered differential amplifier has a value that controls the amount of current correction applied to the negative input of the buffer differential amplifier by the current correction source.
摘要翻译：电路为电路模块提供多模块电流共享。该电路包括具有负和正输入和输出的误差放大器。误差放大器的正输入端连接到参考电压。缓冲差分放大器具有连接到误差放大器的负输入的输出端和正输入端和负输入端。校正电流来源于缓冲差分放大器的负输入。连接到缓冲差分放大器的负输入的电阻器具有控制由当前校正源施加到缓冲差分放大器的负输入端的电流校正量的值。

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