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1. 发明申请

US20070011545A1 SYSTEM AND METHOD FOR TESTING A NAS 审中-公开
标题翻译：用于测试NAS的系统和方法
公开(公告)号：US20070011545A1
公开(公告)日：2007-01-11
申请号：US11308574
申请日：2006-04-08
申请人： CHAO-TSUNG FAN , WEN-CHIEN CHOU , CHIH-CHIANG LIU , CHUN-TE YEH
发明人： CHAO-TSUNG FAN , WEN-CHIEN CHOU , CHIH-CHIANG LIU , CHUN-TE YEH
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/3183 , G01R31/318378
摘要： A system for testing a NAS includes: a data storage device (3) connected with a NAS (6) for storing function test program and test data; a host computer (1) connected with the NAS being used to issue commands for the NAS to self-test itself via the function test program and test data; and at least one USB flash memory (4) connected with the NAS for testing the PCI ports of the NAS. A method for testing a NAS is also disclosed.
摘要翻译：一种用于测试NAS的系统包括：与NAS（6）连接的数据存储设备（3），用于存储功能测试程序和测试数据; 与NAS连接的主机（1）用于发出用于NAS的命令以经由功能测试程序自身测试和测试数据; 以及与NAS连接的至少一个USB闪存（4），用于测试NAS的PCI端口。还公开了一种用于测试NAS的方法。

2. 发明申请

US20120112810A1 CLOCK DE-SKEWING DELAY LOCKED LOOP CIRCUIT 有权
标题翻译：时钟锁定延迟锁定环路
公开(公告)号：US20120112810A1
公开(公告)日：2012-05-10
申请号：US13158697
申请日：2011-06-13
申请人： JINN-SHYAN WANG , CHUN-YUAN CHENG , CHIH-CHIANG LIU
发明人： JINN-SHYAN WANG , CHUN-YUAN CHENG , CHIH-CHIANG LIU
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A clock de-skewing delay locked loop circuit is revealed. In the clock de-skewing delay locked loop circuit, a timing control circuit generates a first and a second clock signals according to an external and an internal clock signal. A clock delay line delays the first clock signal or the external clock signal to generate delay signals. A delay mirror circuit synchronizes the internal clock signal with the external clock signal. A phase adjustment circuit inverts the internal clock signal according to the phase difference. An inverting buffer circuit buffers the external clock signal or the first clock signal for adding an initial delay time so as to make a duty cycle of internal clock signal and of the external clock signal complement each other. Thus the duty cycle of the external clock signal in the proposed circuit is not necessarily 50%.
摘要翻译：揭示了时钟去偏移延迟锁相环电路。在时钟去偏移延迟锁定环电路中，定时控制电路根据外部和内部时钟信号产生第一和第二时钟信号。时钟延迟线延迟第一时钟信号或外部时钟信号以产生延迟信号。延迟镜电路将内部时钟信号与外部时钟信号同步。相位调整电路根据相位差反转内部时钟信号。反相缓冲电路缓冲外部时钟信号或第一时钟信号以增加初始延迟时间，以使内部时钟信号和外部时钟信号的占空比相互补充。因此，所提出的电路中的外部时钟信号的占空比不一定是50％。

3. 发明申请

US20090108864A1 SYSTEM AND METHOD FOR TESTING AN OPERATING CONDITION OF LEDS ON A MOTHERBOARD 失效
标题翻译：用于测试LED灯在操作台上的操作条件的系统和方法
公开(公告)号：US20090108864A1
公开(公告)日：2009-04-30
申请号：US12169638
申请日：2008-07-09
申请人： CHIH-CHIANG LIU , WEI-YUAN CHEN
发明人： CHIH-CHIANG LIU , WEI-YUAN CHEN
IPC分类号： G01R31/27
CPC分类号： G01R31/2635 , G01R31/27
摘要： A computer-implemented method for testing an operating condition of light emitting diodes (LEDs) on a motherboard includes assigning an LED identification for each LED according to positions of the LEDs on the motherboard, selecting a first LED identification for a first LED and a second LED identification for a second LED, setting the first LED in a bright state, the second LED in a dim state, and any remaining LEDs in a flicker state, and controlling the LEDs to operate. The method further includes determining whether the total count of the LEDs in the bright state is equal to one, and whether the total count of the LEDs in the dim state is equal to one, comparing the first LED identification input with the first LED identification, and comparing the second LED identification input with the LED identification, and reporting a comparison result.
摘要翻译：用于测试主板上的发光二极管（LED）的操作状态的计算机实现的方法包括根据主板上的LED的位置为每个LED分配LED标识，为第一LED选择第一LED标识和第二LED标识第二个LED的LED识别，将第一个LED置于亮状态，第二个LED处于昏暗状态，任何剩余的LED处于闪烁状态，并控制LED的工作。该方法还包括确定亮状态中的LED的总计数是否等于1，以及在暗状态下的LED的总计数是否等于1，将第一LED识别输入与第一LED标识进行比较，并将第二LED识别输入与LED识别进行比较，并报告比较结果。

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