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1. 发明申请

US20110065251A1 METHOD FOR FABRICATING STORAGE NODE ELECTRODE IN SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中制作储存节点电极的方法
公开(公告)号：US20110065251A1
公开(公告)日：2011-03-17
申请号：US12834135
申请日：2010-07-12
申请人： Byung Soo Eun
发明人： Byung Soo Eun
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： A method for fabricating a storage node electrode in a semiconductor device includes: performing a primary high density plasma (HDP) process to form a first HDP oxide film over an etch stop film; performing a secondary HDP process to form a second HDP oxide film on the first HDP oxide film; forming a support film over the second HDP oxide film; performing a tertiary HDP process to form a third HDP oxide film over the support film; forming a storage node electrode on an exposed surface of the storage node contact hole; partially removing the third HDP oxide film and the support film so that a support pattern supporting the storage node electrode is formed; and exposing an outer surface of the storage node electrode by removing the second HDP oxide film and the first HDP oxide film.
摘要翻译：一种在半导体器件中制造存储节点电极的方法包括：执行初级高密度等离子体（HDP）工艺以在蚀刻停止膜上形成第一HDP氧化物膜; 执行二次HDP工艺以在第一HDP氧化物膜上形成第二HDP氧化物膜; 在所述第二HDP氧化物膜上形成支撑膜; 执行三次HDP处理以在支撑膜上形成第三HDP氧化物膜; 在所述存储节点接触孔的暴露表面上形成存储节点电极; 部分地去除第三HDP氧化物膜和支撑膜，从而形成支撑存储节点电极的支撑图案; 并且通过去除第二HDP氧化物膜和第一HDP氧化物膜来暴露存储节点电极的外表面。

2. 发明申请

US20100078757A1 SEMICONDUCTOR DEVICE HAVING RECESS GATE AND ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：具有收缩门和隔离结构的半导体器件及其制造方法
公开(公告)号：US20100078757A1
公开(公告)日：2010-04-01
申请号：US12342648
申请日：2008-12-23
申请人： Byung Soo Eun
发明人： Byung Soo Eun
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232 , H01L27/10876 , H01L29/66621
摘要： Disclosed herein is a semiconductor device including an isolation structure and a recess gate and a method for fabricating the same. The method for fabricating a semiconductor device includes: forming a trench by selectively etching an isolation region of a semiconductor substrate to define an active region; forming a first SOD partially filling the trench; forming a stress shielding layer, which is denser than the first SOD, over the first SOD; forming a second SOD that fills the trench over the first SOD including the stress shielding layer; forming a recess groove by selectively etching a portion of the active region, wherein an upper surface of the first SOD is spaced downwardly from a bottom of the recess groove, and an upper surface of the stress shielding layer is spaced upwardly from the bottom of the recessed groove; and forming a gate of a transistor that fills the recess groove.
摘要翻译：本文公开了包括隔离结构和凹槽的半导体器件及其制造方法。制造半导体器件的方法包括：通过选择性地蚀刻半导体衬底的隔离区域来形成沟槽，以限定有源区; 形成部分填充沟槽的第一SOD; 在第一SOD上形成比第一SOD更致密的应力屏蔽层; 形成第二SOD，其填充包括应力屏蔽层在内的第一SOD上的沟槽; 通过选择性蚀刻所述有源区域的一部分来形成凹槽，其中所述第一SOD的上表面与所述凹槽的底部间隔开，并且所述应力屏蔽层的上表面与所述凹槽的底部间隔开凹槽; 以及形成填充所述凹槽的晶体管的栅极。

3. 发明申请

US20080318407A1 Method for Forming Storage Electrode of Semiconductor Memory Device 有权
标题翻译：形成半导体存储器件存储电极的方法
公开(公告)号：US20080318407A1
公开(公告)日：2008-12-25
申请号：US12049024
申请日：2008-03-14
申请人： Byung Soo Eun
发明人： Byung Soo Eun
IPC分类号： H01L21/44
CPC分类号： H01L27/10855
摘要： In order to form a storage electrode of a semiconductor memory device, an interlayer dielectric layer is formed on a semiconductor substrate having a bit line thereon. A contact hole exposing the semiconductor substrate is formed by patterning the interlayer dielectric layer. A polysilicon layer is etched to a predetermined thickness using polysilicon etching gas after the polysilicon layer is deposited. An over-etch process is performed relative to the polysilicon layer, and then a storage node contact having a planarized surface is formed in the contact hole by performing an etching process for planarizing the surface of the polysilicon layer. A mold insulating layer is formed on the resultant structure, in which the mold insulating layer exposes an area where the storage node contact is formed. A storage electrode coupled to the storage node contact is formed.
摘要翻译：为了形成半导体存储器件的存储电极，在其上具有位线的半导体衬底上形成层间电介质层。通过图案化层间电介质层形成露出半导体衬底的接触孔。在沉积多晶硅层之后，使用多晶硅蚀刻气体将多晶硅层蚀刻至预定厚度。相对于多晶硅层进行过蚀刻工艺，然后通过执行用于使多晶硅层的表面平坦化的蚀刻工艺，在接触孔中形成具有平坦化表面的存储节点接触。在所得结构上形成模具绝缘层，其中模具绝缘层暴露存储节点接触形成的区域。形成连接到存储节点接点的存储电极。

4. 发明申请

US20080067685A1 Semiconductor Device Manufacturing Method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：US20080067685A1
公开(公告)日：2008-03-20
申请号：US11761592
申请日：2007-06-12
申请人： Byung Soo Eun
发明人： Byung Soo Eun
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L21/76837 , H01L21/76829
摘要： A semiconductor device manufacturing method includes forming a conductive layer pattern on a semiconductor substrate, forming a seed layer having a high silicon content ratio on the conductive layer pattern, and forming an interlayer dielectric to bury the conductive layer pattern on the seed layer.
摘要翻译：一种半导体器件制造方法，包括在半导体衬底上形成导电层图案，在导电层图案上形成硅含量比高的晶种层，以及形成层间电介质以将导电层图案埋在种子层上。

5. 发明授权

US08169048B2 Isolation structure in a memory device 有权
标题翻译：存储器件中的隔离结构
公开(公告)号：US08169048B2
公开(公告)日：2012-05-01
申请号：US13023992
申请日：2011-02-09
申请人： Byung Soo Eun
发明人： Byung Soo Eun
IPC分类号： H01L21/70
CPC分类号： H01L21/76229
摘要： An isolation structure in a memory device and a method for fabricating the isolation structure. In the method, a first trench is formed in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. A liner layer comprising a silicon nitride layer is formed on the first and second trenches. A spin on dielectric (SOD) layer comprising polysilazane is formed on the liner layer so as to fill the first and second trenches. A portion of the SOD layer filling the second trench is removed. A portion of the silicon nitride layer, which is disposed on the second trench and is exposed after the removing of the portion of the SOD layer, is oxidized using oxygen plasma and heat generated from the plasma. A high density plasma (HDP) oxide layer is formed to fill the second trench.
摘要翻译：存储器件中的隔离结构和用于制造隔离结构的方法。在该方法中，在半导体衬底的单元区域和半导体衬底的周边区域中形成第二沟槽，形成第一沟槽。在第一和第二沟槽上形成包含氮化硅层的衬里层。在衬垫层上形成包含聚硅氮烷的在电介质（SOD）层上的旋转以填充第一和第二沟槽。去除填充第二沟槽的SOD层的一部分。设置在第二沟槽上并且在去除SOD层的部分之后露出的氮化硅层的一部分被氧等离子体和从等离子体产生的热量氧化。形成高密度等离子体（HDP）氧化物层以填充第二沟槽。

6. 发明申请

US20110127634A1 Isolation Structure in a Memory Device 有权
标题翻译：存储器件中的隔离结构
公开(公告)号：US20110127634A1
公开(公告)日：2011-06-02
申请号：US13023992
申请日：2011-02-09
申请人： Byung Soo Eun
发明人： Byung Soo Eun
IPC分类号： H01L29/06
CPC分类号： H01L21/76229
摘要： An isolation structure in a memory device and a method for fabricating the isolation structure. In the method, a first trench is formed in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. A liner layer comprising a silicon nitride layer is formed on the first and second trenches. A spin on dielectric (SOD) layer comprising polysilazane is formed on the liner layer so as to fill the first and second trenches. A portion of the SOD layer filling the second trench is removed. A portion of the silicon nitride layer, which is disposed on the second trench and is exposed after the removing of the portion of the SOD layer, is oxidized using oxygen plasma and heat generated from the plasma. A high density plasma (HDP) oxide layer is formed to fill the second trench.
摘要翻译：存储器件中的隔离结构和用于制造隔离结构的方法。在该方法中，在半导体衬底的单元区域和半导体衬底的周边区域中形成第二沟槽，形成第一沟槽。在第一和第二沟槽上形成包含氮化硅层的衬里层。在衬垫层上形成包含聚硅氮烷的在电介质（SOD）层上的旋转以填充第一和第二沟槽。去除填充第二沟槽的SOD层的一部分。设置在第二沟槽上并且在去除SOD层的部分之后露出的氮化硅层的一部分被氧等离子体和从等离子体产生的热量氧化。形成高密度等离子体（HDP）氧化物层以填充第二沟槽。

7. 发明授权

US07902037B2 Isolation structure in memory device and method for fabricating the same 失效
标题翻译：存储器件中的隔离结构及其制造方法
公开(公告)号：US07902037B2
公开(公告)日：2011-03-08
申请号：US12329709
申请日：2008-12-08
申请人： Byung Soo Eun
发明人： Byung Soo Eun
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L27/1052 , H01L27/10894 , H01L27/10897
摘要： A method for fabricating an isolation structure in a memory device includes forming a first trench in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. The method also includes oxidating the surface of the first and second trenches to form a sidewall oxide layer; depositing a tetraethylorthosilicate(TEOS) layer on the sidewall oxide layer; forming a silicon nitride layer and a silicon oxide layer on the TEOS layer; selectively removing portions of the silicon nitride and silicon oxide layers on the second trench to expose a portion of the underlying TEOS layer; coating a flowable insulation layer that fills the first and second trenches; and curing the flowable insulation layer.
摘要翻译：一种用于在存储器件中制造隔离结构的方法包括在半导体衬底的单元区域中形成第一沟槽和在半导体衬底的周边区域中形成第二沟槽。该方法还包括氧化第一和第二沟槽的表面以形成侧壁氧化物层; 在所述侧壁氧化物层上沉积原硅酸四乙酯（TEOS）层; 在TEOS层上形成氮化硅层和氧化硅层; 选择性地去除第二沟槽上的氮化硅和氧化硅层的部分以暴露下面的TEOS层的一部分; 涂覆填充所述第一和第二沟槽的可流动绝缘层; 并固化可流动的绝缘层。

8. 发明申请

US20100330804A1 Method for Fabricating Bitline in Semiconductor Device 失效
标题翻译：半导体器件中位线的制作方法
公开(公告)号：US20100330804A1
公开(公告)日：2010-12-30
申请号：US12639779
申请日：2009-12-16
申请人： Byung Soo Eun
发明人： Byung Soo Eun
IPC分类号： H01L21/768
CPC分类号： H01L21/76834 , H01L21/76832 , H01L27/10885
摘要： A method of a fabricating a bitline in a semiconductor device, comprising: forming an interlayer insulation layer that defines a bitline contact hole on a semiconductor substrate; forming a contact layer to fill the bitline contact hole; forming a bitline contact by planarizing the contact layer; forming a bitline stack aligned with the bitline contact; forming a high aspect ratio process (HARP) layer that extends along the bitline stack and the interlayer insulation layer while covering a seam exposed in a side portion of the bitline stack by excessive planarization during formation of the bitline contact; and forming an interlayer gap-filling insulation layer on the HARP layer that gap-fills the entire bitline stack.
摘要翻译：一种在半导体器件中制造位线的方法，包括：在半导体衬底上形成限定位线接触孔的层间绝缘层; 形成接触层以填充位线接触孔; 通过平坦化接触层形成位线接触; 形成与所述位线触点对准的位线堆叠; 形成沿着位线堆叠和层间绝缘层延伸的高纵横比工艺（HARP）层，同时在形成位线接触期间通过过度平坦化覆盖在位线堆叠的侧部暴露的接缝; 并在HARP层上形成间隙填充绝缘层，间隙填充整个位线堆叠。

9. 发明申请

US20100159700A1 Method for Fabricating Cylinder Type Capacitor 失效
标题翻译：制造圆柱型电容器的方法
公开(公告)号：US20100159700A1
公开(公告)日：2010-06-24
申请号：US12492905
申请日：2009-06-26
申请人： Byung Soo Eun
发明人： Byung Soo Eun
IPC分类号： H01L21/306
CPC分类号： H01L21/31144 , H01L27/10852 , H01L28/91
摘要： A method for fabricating a cylinder type capacitor includes forming connection contacts passing through a lower layer over a semiconductor substrate; forming a mold layer covering the connection contacts; forming a first floated pinning layer with a stress in a first direction over the mold layer; forming a second floated pinning layer for stress relief with a stress in a second direction over the first floated pinning layer, said second direction being opposite to the first direction; forming opening holes passing through the first and second floated pinning layers and the mold layer and exposing the connection contacts; forming storage nodes following a profile of the opening holes; removing portions of the first and second floated pinning layers to form a floated pinning layer pattern, the floated pinning layer pattern exposing a portion of the mold layer and contacting upper tips of the storage nodes; exposing outer walls of the storage nodes by selectively removing the exposed mold layer; and forming a dielectric layer and an upper electrode over the storage node.
摘要翻译：制造圆柱型电容器的方法包括：形成通过半导体衬底上的下层的连接触点; 形成覆盖所述连接触点的模具层; 在所述模制层上形成在第一方向上具有应力的第一浮起钉扎层; 形成第二浮起钉扎层，用于在第一浮起钉扎层上沿第二方向施加应力消除，所述第二方向与第一方向相反; 形成通过所述第一和第二浮起的钉扎层和所述模具层并使所述连接触头暴露的开孔; 沿着开孔的轮廓形成储存节点; 去除所述第一和第二浮起的钉扎层的部分以形成漂浮的钉扎层图案，所述浮起的钉扎层图案暴露所述模制层的一部分并接触所述存储节点的上端; 通过选择性地去除暴露的模制层来暴露存储节点的外壁; 以及在所述存储节点上形成介电层和上电极。

10. 发明授权

US07736972B2 Method for forming storage electrode of semiconductor memory device 有权
标题翻译：形成半导体存储器件的存储电极的方法
公开(公告)号：US07736972B2
公开(公告)日：2010-06-15
申请号：US12049024
申请日：2008-03-14
申请人： Byung Soo Eun
发明人： Byung Soo Eun
IPC分类号： H01L21/8242
CPC分类号： H01L27/10855
摘要： In order to form a storage electrode of a semiconductor memory device, an interlayer dielectric layer is formed on a semiconductor substrate having a bit line thereon. A contact hole exposing the semiconductor substrate is formed by patterning the interlayer dielectric layer. A polysilicon layer is etched to a predetermined thickness using polysilicon etching gas after the polysilicon layer is deposited. An over-etch process is performed relative to the polysilicon layer, and then a storage node contact having a planarized surface is formed in the contact hole by performing an etching process for planarizing the surface of the polysilicon layer. A mold insulating layer is formed on the resultant structure, in which the mold insulating layer exposes an area where the storage node contact is formed. A storage electrode coupled to the storage node contact is formed.
摘要翻译：为了形成半导体存储器件的存储电极，在其上具有位线的半导体衬底上形成层间电介质层。通过图案化层间电介质层形成露出半导体衬底的接触孔。在沉积多晶硅层之后，使用多晶硅蚀刻气体将多晶硅层蚀刻至预定厚度。相对于多晶硅层进行过蚀刻工艺，然后通过执行用于使多晶硅层的表面平坦化的蚀刻工艺在接触孔中形成具有平坦化表面的存储节点接触。在所得结构上形成模具绝缘层，其中模具绝缘层暴露存储节点接触形成的区域。形成连接到存储节点接点的存储电极。

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