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1. 发明授权

US07420496B2 Digital/analog converting apparatus with high resolution 失效
标题翻译：具有高分辨率的数字/模拟转换装置
公开(公告)号：US07420496B2
公开(公告)日：2008-09-02
申请号：US11565531
申请日：2006-11-30
申请人： Byung Hoon Kim , Taek Soo Kim , Youn Joong Lee , Chan Woo Park
发明人： Byung Hoon Kim , Taek Soo Kim , Youn Joong Lee , Chan Woo Park
IPC分类号： H03M1/66
CPC分类号： H03M1/682 , H03M1/765
摘要： A high resolution digital/analog converting apparatus for a spatial optical modulator includes a resistor string including a plurality of resistors connected to each other in series between operating voltage terminals to divide operating voltages into a plurality of voltages using the plural resistors, a decoder to provide switching signals corresponding to digital signals, and a switch unit to select two voltages from the plural voltages divided by the resistor string according to the switching signal of the decoder. The two voltages are adjacent to each other. Moreover, the digital/analog converting apparatus may include a digital/analog converter to perform a digital/analog conversion of the two voltages.
摘要翻译：用于空间光学调制器的高分辨率数字/模拟转换装置包括：电阻串，包括串联连接在工作电压端子之间的多个电阻器，用于使用多个电阻将工作电压分成多个电压;解码器，与数字信号对应的切换信号，以及开关单元，根据解码器的切换信号从由电阻串划分的多个电压中选择两个电压。两个电压彼此相邻。此外，数字/模拟转换装置可以包括数字/模拟转换器，以执行两个电压的数字/模拟转换。

2. 发明授权

US07330143B2 Digital/analog converter 失效
标题翻译：数字/模拟转换器
公开(公告)号：US07330143B2
公开(公告)日：2008-02-12
申请号：US11428363
申请日：2006-06-30
申请人： Byung Hoon Kim , Won Tae Choi , Youn Joong Lee , Chan Woo Park
发明人： Byung Hoon Kim , Won Tae Choi , Youn Joong Lee , Chan Woo Park
IPC分类号： H03M1/78
CPC分类号： H03M1/682
摘要： The present invention relates to a digital/analog converter. The digital/analog converter includes a divided-voltage generating section that divides a reference supply voltage through the voltage distribution; a decoder section that receives a digital signal so as to output a decoded selection signal; a first divided-voltage selecting section that selects and outputs a plurality of divided voltages among the divided-voltages generated from the divided-voltage generating section on the basis of the selection signal output from the decoder section; a second divided-voltage selecting section that selects and outputs a plurality of divided-voltages among the divided-voltages output from the first divided-voltage selecting section on the basis of the selection signal output from the decoder section; a divided-voltage storing section that charges and discharges the plurality of divided-voltages output from the second divided-voltage selecting section; a third divided-voltage selecting section that selects a predetermined voltage among the divided-voltages discharged from the divided-voltages storing section on the basis of the selection signal output from the decoder; and a voltage output section that outputs the predetermined voltage selected from the third divided-voltage selecting section.
摘要翻译：本发明涉及数字/模拟转换器。该数/模转换器包括分压电压产生部分，该分压产生部分通过电压分配来划分参考电源电压; 解码器部分，其接收数字信号以输出解码的选择信号; 第一分压电压选择部分，根据从解码器部分输出的选择信号，在从分压产生部分产生的分压中选择和输出多个分压; 第二分压选择部，根据从解码部输出的选择信号，选择并输出从第一分压电压选择部输出的分压电压中的多个分压; 分压电压存储部，对从第二分压选择部输出的多个分压进行充放电; 第三分压电压选择部，其根据从解码器输出的选择信号，选择从分压存储部放电的分压中的规定电压; 以及电压输出部，输出从第三分压选择部选择的预定电压。

3. 发明申请

US20070030050A1 TEMPERATURE COMPENSATED BIAS SOURCE CIRCUIT 审中-公开
标题翻译：温度补偿偏置电源电路
公开(公告)号：US20070030050A1
公开(公告)日：2007-02-08
申请号：US11422574
申请日：2006-06-06
申请人： Youn Joong Lee , Won Tae Choi , Chan Woo Park , Byung Hoon Kim
发明人： Youn Joong Lee , Won Tae Choi , Chan Woo Park , Byung Hoon Kim
IPC分类号： H01L35/00
CPC分类号： G05F3/30
摘要： The present invention relates to a temperature-compensated bias source circuit. The temperature-compensated bias source circuit includes a bandgap reference circuit that outputs a first temperature-compensated reference voltage and a second reference voltage having a positive slope with respect to temperature; a voltage/current converter that converts the first and second reference voltages into a reference current; and an output buffer that is connected to the bandgap reference circuit and the voltage/current converter and buffers the first and second reference voltages, output by the bandgap reference circuit, so as to output to the voltage/current converter.
摘要翻译：本发明涉及温度补偿偏置源电路。温度补偿偏置源电路包括带隙参考电路，其输出相对于温度具有正斜率的第一温度补偿参考电压和第二参考电压; 电压/电流转换器，其将第一和第二参考电压转换为参考电流; 以及输出缓冲器，其连接到带隙基准电路和电压/电流转换器，并且缓冲由带隙基准电路输出的第一和第二参考电压，以输出到电压/电流转换器。

4. 发明授权

US07414441B2 Output buffer circuit 失效
标题翻译：输出缓冲电路
公开(公告)号：US07414441B2
公开(公告)日：2008-08-19
申请号：US11422568
申请日：2006-06-06
申请人： Youn Joong Lee , Won Tae Choi , Chan Woo Park , Byung Hoon Kim
发明人： Youn Joong Lee , Won Tae Choi , Chan Woo Park , Byung Hoon Kim
IPC分类号： H03K3/00
CPC分类号： H03F3/347 , H03F1/301 , H03F1/303 , H03F3/45753 , H03F2203/45212
摘要： An output buffer circuit includes an input stage of which one end receives an input voltage and the other end receives an output voltage; a class AB output stage that increases a current flowing in the output stage when the difference between the input and output voltages is larger than 0; a floating current source that biases the class AB output stage; a summing circuit that is connected to the input stage, the floating current source, and the class AB output stage so as to sum up the current supplied from the input stage and the internal current supplied from the floating current source; and an offset compensating circuit that is connected to the input stage and is composed of a plurality of switching elements and resistors so as to detect an offset voltage to compensate.
摘要翻译：输出缓冲电路包括输入级，其一端接收输入电压，另一端接收输出电压; AB类输出级，当输入和输出电压之间的差大于0时，增加在输出级中流动的电流; 偏置AB类输出级的浮动电流源; 连接到输入级，浮动电流源和AB类输出级的求和电路，以便对从输入级提供的电流和从浮动电流源提供的内部电流求和; 以及偏移补偿电路，其连接到输入级，并且由多个开关元件和电阻器组成，以便检测偏移电压以进行补偿。

5. 发明授权

US07482845B2 Output buffer circuit 失效
标题翻译：输出缓冲电路
公开(公告)号：US07482845B2
公开(公告)日：2009-01-27
申请号：US11469219
申请日：2006-08-31
申请人： Youn Joong Lee , Won Tae Choi , Chan Woo Park , Byung Hoon Kim
发明人： Youn Joong Lee , Won Tae Choi , Chan Woo Park , Byung Hoon Kim
IPC分类号： H03B1/00
CPC分类号： H03F3/45219 , H03F3/3022 , H03F3/45183 , H03F2203/45118 , H03F2203/45248 , H03F2203/45366 , H03F2203/45536 , H03F2203/45626
摘要： Provided is an output buffer circuit having a slew rate increasing part configured with a switching element. The output buffer circuit can obtain an output voltage having a high slew rate even though a smaller amount of a bias current than that required in a conventional output buffer is used. Therefore, the output buffer circuit can reduce power consumption. In the output buffer circuit with a compensation capacitive load, an input part has two input terminal receiving differential input voltage signals, and an output part increases a gain of the differential input voltages. A current source biases the output part, and a slew rate increasing part is connected to the output part and the compensation capacitive load. The slew rate increasing part includes a switching element to increase a slew rate of the output buffer circuit.
摘要翻译：提供一种具有由开关元件构成的压摆率增加部分的输出缓冲器电路。即使使用比常规输出缓冲器中所需的偏置电流更小的量，输出缓冲器电路也可以获得具有高转换速率的输出电压。因此，输出缓冲电路可以降低功耗。在具有补偿容性负载的输出缓冲电路中，输入部分具有两个输入端接收差分输入电压信号，输出部分增加差分输入电压的增益。电流源偏置输出部分，并且转换速率增加部分连接到输出部分和补偿电容性负载。压摆率增加部分包括提高输出缓冲电路的转换速率的开关元件。

6. 发明授权

US07375669B2 Digital/analog converter 失效
标题翻译：数字/模拟转换器
公开(公告)号：US07375669B2
公开(公告)日：2008-05-20
申请号：US11379428
申请日：2006-04-20
申请人： Byung Hoon Kim , Won Tae Choi , Youn Joong Lee , Chan Woo Park
发明人： Byung Hoon Kim , Won Tae Choi , Youn Joong Lee , Chan Woo Park
IPC分类号： H03M1/66
CPC分类号： H03M1/682 , H03M1/765
摘要： A digital/analog converter includes a first divided-voltage generating section which divides a reference supply voltage through the voltage distribution, a decoder section which receives a digital signal so as to output a decoded selection signal, a first divided-voltage selecting section which selects and outputs a plurality of divided voltages among the divided voltages generated from the first divided-voltage generating section on the basis of the selection signal output from the decoder section, a second divided-voltage selecting section which selects and outputs a plurality of divided voltages among the divided-voltages output from the first divided-voltage selecting section on the basis of the selection signal output from the decoder section, a second divided-voltage generating section which divides the plurality of divided-voltages output from the second divided-voltage selecting section, a third divided-voltage selecting section which selects a predetermined voltage among the divided-voltages output from the second divided-voltages generating section on the basis of the selection signal output from the decoder, and a voltage output section which outputs the predetermined voltage selected from the third divided-voltage selecting section.
摘要翻译：数字/模拟转换器包括：第一分压产生部，其通过电压分布分割参考电源电压;解码器部，其接收数字信号以输出解码的选择信号;第一分压电压选择部，其选择并且根据从解码器部分输出的选择信号，在从第一分压产生部分产生的划分电压之间输出多个分压，第二分压选择部分选择并输出多个分压电压基于从解码器部分输出的选择信号从第一分压电压选择部分输出的分压;第二分压产生部分，从第二分压选择部分输出的多个分压，，第三分压选择部，其选择d中的预定电压基于从解码器输出的选择信号从第二分压产生部分输出的分压，以及输出从第三分压选择部选择的预定电压的电压输出部。

7. 发明申请

US20070080723A1 OUTPUT BUFFER CIRCUIT 失效
标题翻译：输出缓冲电路
公开(公告)号：US20070080723A1
公开(公告)日：2007-04-12
申请号：US11469219
申请日：2006-08-31
申请人： Youn Joong Lee , Won Tae Choi , Chan Woo Park , Byung Hoon Kim
发明人： Youn Joong Lee , Won Tae Choi , Chan Woo Park , Byung Hoon Kim
IPC分类号： H03B1/00
CPC分类号： H03F3/45219 , H03F3/3022 , H03F3/45183 , H03F2203/45118 , H03F2203/45248 , H03F2203/45366 , H03F2203/45536 , H03F2203/45626
摘要： Provided is an output buffer circuit having a slew rate increasing part configured with a switching element. The output buffer circuit can obtain an output voltage having a high slew rate even though a smaller amount of a bias current than that required in a conventional output buffer is used. Therefore, the output buffer circuit can reduce power consumption. In the output buffer circuit with a compensation capacitive load, an input part has two input terminal receiving differential input voltage signals, and an output part increases a gain of the differential input voltages. A current source biases the output part, and a slew rate increasing part is connected to the output part and the compensation capacitive load. The slew rate increasing part includes a switching element to increase a slew rate of the output buffer circuit.
摘要翻译：提供一种具有由开关元件构成的压摆率增加部分的输出缓冲器电路。即使使用比常规输出缓冲器中所需的偏置电流更小的量，输出缓冲器电路也可以获得具有高转换速率的输出电压。因此，输出缓冲电路可以降低功耗。在具有补偿容性负载的输出缓冲电路中，输入部分具有两个输入端接收差分输入电压信号，输出部分增加差分输入电压的增益。电流源偏置输出部分，并且转换速率增加部分连接到输出部分和补偿电容性负载。压摆率增加部分包括提高输出缓冲电路的转换速率的开关元件。

8. 发明授权

US08263964B2 Three-dimensional nanodevices including nanostructures 有权
标题翻译：包括纳米结构在内的三维纳米器件
公开(公告)号：US08263964B2
公开(公告)日：2012-09-11
申请号：US12672995
申请日：2008-05-19
申请人： Han Young Yu , Byung Hoon Kim , An Soon Kim , In Bok Baek , Chil Seong Ah , Jong Heon Yang , Chan Woo Park , Chang Geun Ahn
发明人： Han Young Yu , Byung Hoon Kim , An Soon Kim , In Bok Baek , Chil Seong Ah , Jong Heon Yang , Chan Woo Park , Chang Geun Ahn
IPC分类号： H01L29/06
CPC分类号： H01J49/4205 , B81B7/0025 , B81B2201/0214 , B81B2201/0271 , B82Y10/00 , B82Y40/00 , G01N2291/0257 , H01J49/0018 , H01L29/0673 , H01L29/7613 , H01L29/775 , H03H2009/02314
摘要： Provided are three-dimensional (3D) nanodevices including 3D nanostructures. The 3D nanodevice includes at least one nanostructure, each nanostructure including an oscillation portion floating over a substrate and support portions for supporting both lengthwise end portions of the oscillation portion, supports disposed on the substrate to support the support portions of each of the nanostructures, at least one controller disposed at an upper portion of the substrate, a lower portion of the substrate, or both the upper and lower portions of the substrate to control each of the nanostructures, and a sensing unit disposed on each of the oscillation portions to sense an externally supplied adsorption material. Thus, unlike in a typical planar device, generation of impurities between a nanodevice and a substrate can be reduced, and mechanical vibration can be caused. In particular, since 3D nanostructures have mechanical and electrical characteristics, 3D nanodevices including new 3D nanostructures can be provided using nano-electro-mechanical systems (NEMS). Also, a single electron device, a spin device, or a single electron transistor (SET)-field effect transistor (FET) hybrid device can be formed using a simple process unlike in planar devices.
摘要翻译：提供了三维（3D）纳米器件，包括3D纳米结构。 3D纳米装置包括至少一个纳米结构，每个纳米结构包括漂浮在基板上的振荡部分和支撑部分，用于支撑振荡部分的两个纵向端部，支撑件设置在基板上以支撑每个纳米结构的支撑部分，设置在基板的上部，基板的下部或基板的上部和下部的至少一个控制器，以控制每个纳米结构;以及感测单元，设置在每个振荡部分上以感测外部供应的吸附材料。因此，与典型的平面器件不同，可以减少纳米器件与衬底之间的杂质的产生，并且可能引起机械振动。特别地，由于3D纳米结构具有机械和电学特性，可以使用纳米机电系统（NEMS）提供包括新的3D纳米结构的3D纳米器件。此外，可以使用与平面器件不同的简单工艺来形成单电子器件，自旋器件或单电子晶体管（SET）场效应晶体管（FET）混合器件。

9. 发明申请

US20110193052A1 THREE-DIMENSIONAL NANODEVICES INCLUDING NANOSTRUCTURES 有权
标题翻译：包括纳米结构的三维纳米器件
公开(公告)号：US20110193052A1
公开(公告)日：2011-08-11
申请号：US12672995
申请日：2008-05-19
申请人： Han Young Yu , Byung Hoon Kim , An Soon Kim , In Bok Baek , Chil Seong Ah , Jong Heon Yang , Chan Woo Park , Chang Geun Ahn
发明人： Han Young Yu , Byung Hoon Kim , An Soon Kim , In Bok Baek , Chil Seong Ah , Jong Heon Yang , Chan Woo Park , Chang Geun Ahn
IPC分类号： H01L29/06 , B82Y99/00
CPC分类号： H01J49/4205 , B81B7/0025 , B81B2201/0214 , B81B2201/0271 , B82Y10/00 , B82Y40/00 , G01N2291/0257 , H01J49/0018 , H01L29/0673 , H01L29/7613 , H01L29/775 , H03H2009/02314
摘要： Provided are three-dimensional (3D) nanodevices including 3D nanostructures. The 3D nanodevice includes at least one nanostructure, each nanostructure including an oscillation portion floating over a substrate and support portions for supporting both lengthwise end portions of the oscillation portion, supports disposed on the substrate to support the support portions of each of the nanostructures, at least one controller disposed at an upper portion of the substrate, a lower portion of the substrate, or both the upper and lower portions of the substrate to control each of the nanostructures, and a sensing unit disposed on each of the oscillation portions to sense an externally supplied adsorption material. Thus, unlike in a typical planar device, generation of impurities between a nanodevice and a substrate can be reduced, and mechanical vibration can be caused. In particular, since 3D nanostructures have mechanical and electrical characteristics, 3D nanodevices including new 3D nanostructures can be provided using nano-electro-mechanical systems (NEMS). Also, a single electron device, a spin device, or a single electron transistor (SET)-field effect transistor (FET) hybrid device can be formed using a simple process unlike in planar devices.
摘要翻译：提供了三维（3D）纳米器件，包括3D纳米结构。 3D纳米装置包括至少一个纳米结构，每个纳米结构包括漂浮在基板上的振荡部分和支撑部分，用于支撑振荡部分的两个纵向端部，支撑件设置在基板上以支撑每个纳米结构的支撑部分，设置在基板的上部，基板的下部或基板的上部和下部的至少一个控制器，以控制每个纳米结构;以及感测单元，设置在每个振荡部分上以感测外部供应的吸附材料。因此，与典型的平面器件不同，可以减少纳米器件与衬底之间的杂质的产生，并且可能引起机械振动。特别地，由于3D纳米结构具有机械和电学特性，可以使用纳米机电系统（NEMS）提供包括新的3D纳米结构的3D纳米器件。此外，可以使用与平面器件不同的简单工艺来形成单电子器件，自旋器件或单电子晶体管（SET）场效应晶体管（FET）混合器件。

10. 发明授权

US08283654B2 Nanowire memory 有权
标题翻译：纳米线记忆
公开(公告)号：US08283654B2
公开(公告)日：2012-10-09
申请号：US12621809
申请日：2009-11-19
申请人： Han Young Yu , Byung Hoon Kim , Soon Young Oh , Yong Ju Yun , Yark Yeon Kim , Won Gi Hong
发明人： Han Young Yu , Byung Hoon Kim , Soon Young Oh , Yong Ju Yun , Yark Yeon Kim , Won Gi Hong
IPC分类号： H01L29/06 , H01L35/24 , H01L31/0312 , H01L29/792 , H01L31/0328
CPC分类号： H01L29/775 , B82Y10/00 , H01L27/10873 , H01L29/0665 , H01L29/0673 , H01L29/685
摘要： Provided is a nanowire memory including a source and a drain corresponding to the source, and a nano channel formed to connect the source to the drain. Here, the nano channel includes a nanowire electrically connecting the source to the drain according to voltages of the source and drain, and a nanodot formed on the nanowire and having a plurality of potentials capturing charges. Thus, the nanowire memory has a simple structure, thereby simplifying a process. It can generate multi current levels by adjusting several energy states using gates, operate as a volatile or non-volatile memory by adjusting the gates and the energy level, and include another gate configured to adjust the energy level, resulting in formation of a hybrid structure of volatile and non-volatile memories.
摘要翻译：提供了纳米线存储器，其包括对应于源极的源极和漏极，以及形成为将源极连接到漏极的纳米通道。这里，纳米通道包括根据源极和漏极的电压将源极与漏极电连接的纳米线，以及形成在纳米线上并具有捕获电荷的多个电位的纳米点。因此，纳米线存储器具有简单的结构，从而简化了工艺。它可以通过使用门调节几个能量状态来产生多个电流电平，通过调整栅极和能量水平来操作为易失性或非易失性存储器，并且包括配置成调整能级的另一个门，从而形成混合结构的易失性和非易失性存储器。

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