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1. 发明授权

US08990538B2 Managing memory with limited write cycles in heterogeneous memory systems 有权
标题翻译：在异构存储器系统中以有限的写周期管理存储器
公开(公告)号：US08990538B2
公开(公告)日：2015-03-24
申请号：US12940780
申请日：2010-11-05
申请人： Bruce L. Worthington , Swaroop V. Kavalanekar , Robert P. Fitzgerald , René A. Vega
发明人： Bruce L. Worthington , Swaroop V. Kavalanekar , Robert P. Fitzgerald , René A. Vega
IPC分类号： G06F13/00 , G06F13/28 , G06F11/30 , G06F12/02 , G11C16/34 , G06F12/06
CPC分类号： G06F11/3037 , G06F11/3055 , G06F12/0223 , G06F12/06 , G06F2212/205 , G11C16/349
摘要： A method and a memory manager for managing data storage in a plurality of types of memories. The types of memories may comprise a primary memory, such as DRAM, and a secondary memory, such as a phase change memory (PCM) or Flash memory, which may have a limited lifetime. The memory manager may be part of an operating system and may manage the memories as part of a unified address space. Characteristics of data to be stored in the memories may be used to select between the primary and secondary memories to store the data and move data between the memories. When the data is to be stored in the secondary memory, health information on the secondary memory and characteristics of the data to be stored may be used to select a location within the secondary memory to store the data.
摘要翻译：一种用于管理多种类型的存储器中的数据存储的方法和存储器管理器。存储器的类型可以包括诸如DRAM的主存储器，以及可能具有有限寿命的次要存储器，例如相变存储器（PCM）或闪速存储器。存储器管理器可以是操作系统的一部分，并且可以作为统一地址空间的一部分来管理存储器。要存储在存储器中的数据的特征可以用于在主存储器和次存储器之间选择存储数据并在存储器之间移动数据。当数据要存储在辅助存储器中时，辅助存储器上的健康信息和要存储的数据的特性可以用于选择次存储器内的存储数据的位置。

2. 发明申请

US20120117304A1 MANAGING MEMORY WITH LIMITED WRITE CYCLES IN HETEROGENEOUS MEMORY SYSTEMS 有权
标题翻译：在异质存储器系统中管理具有有限写入周期的存储器
公开(公告)号：US20120117304A1
公开(公告)日：2012-05-10
申请号：US12940780
申请日：2010-11-05
申请人： Bruce L. Worthington , Swaroop V. Kavalanekar , Robert P. Fitzgerald , René A. Vega
发明人： Bruce L. Worthington , Swaroop V. Kavalanekar , Robert P. Fitzgerald , René A. Vega
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F11/3037 , G06F11/3055 , G06F12/0223 , G06F12/06 , G06F2212/205 , G11C16/349
摘要： A method and a memory manager for managing data storage in a plurality of types of memories. The types of memories may comprise a primary memory, such as DRAM, and a secondary memory, such as a phase change memory (PCM) or Flash memory, which may have a limited lifetime. The memory manager may be part of an operating system and may manage the memories as part of a unified address space. Characteristics of data to be stored in the memories may be used to select between the primary and secondary memories to store the data and move data between the memories. When the data is to be stored in the secondary memory, health information on the secondary memory and characteristics of the data to be stored may be used to select a location within the secondary memory to store the data.
摘要翻译：一种用于管理多种类型的存储器中的数据存储的方法和存储器管理器。存储器的类型可以包括诸如DRAM的主存储器，以及可能具有有限寿命的次要存储器，例如相变存储器（PCM）或闪速存储器。存储器管理器可以是操作系统的一部分，并且可以作为统一地址空间的一部分来管理存储器。要存储在存储器中的数据的特征可以用于在主存储器和次存储器之间选择存储数据并在存储器之间移动数据。当数据要存储在辅助存储器中时，辅助存储器上的健康信息和要存储的数据的特性可以用于选择次存储器内的存储数据的位置。

3. 发明授权

US07788435B2 Interrupt redirection with coalescing 有权
标题翻译：中断重定向与合并
公开(公告)号：US07788435B2
公开(公告)日：2010-08-31
申请号：US11971775
申请日：2008-01-09
申请人： Bruce L. Worthington , Goran Marinkovic , Brian Railing , Qi Zhang , Swaroop V. Kavalanekar
发明人： Bruce L. Worthington , Goran Marinkovic , Brian Railing , Qi Zhang , Swaroop V. Kavalanekar
IPC分类号： G06F13/24
CPC分类号： G06F9/4812
摘要： An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The efficiency of processing may be improved by combining multiple interrupt notifications into a single interrupt message to a processor. For some interrupts on a multi-processor computer, such as those signaling completion of an input/output (I/O) operation assigned to a device, the efficiency of processing the interrupt may vary from processor to processor. Processing efficiency and overall computer system operation may be improved by appropriately coalescing interrupt messages within and/or across a plurality of queues, where interrupts are queued on the basis of which processor they target.
摘要翻译：用于多处理器计算机的中断重定向和聚合系统。设备使用通过PCI，PCI-X或PCI Express总线与存储器写入事务通信的预定义消息地址和数据有效负载中断处理器或处理器组。通过将多个中断通知组合成单个中断消息到处理器，可以提高处理效率。对于多处理器计算机上的一些中断，例如那些信令完成分配给设备的输入/输出（I / O）操作），处理器的处理效率可能随处理器而异。可以通过适当地聚合多个队列内和/或跨多个队列的中断消息来改善处理效率和整体计算机系统操作，其中中断基于他们所针对的哪个处理器进行排队。

4. 发明申请

US20090177829A1 INTERRUPT REDIRECTION WITH COALESCING 有权
标题翻译：中断重定向与COALESCING
公开(公告)号：US20090177829A1
公开(公告)日：2009-07-09
申请号：US11971775
申请日：2008-01-09
申请人： Bruce L. Worthington , Goran Marinkovic , Brian Railing , Qi Zhang , Swaroop V. Kavalanekar
发明人： Bruce L. Worthington , Goran Marinkovic , Brian Railing , Qi Zhang , Swaroop V. Kavalanekar
IPC分类号： G06F13/24 , G06F9/44
CPC分类号： G06F9/4812
摘要： An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The efficiency of processing may be improved by combining multiple interrupt notifications into a single interrupt message to a processor. For some interrupts on a multi-processor computer, such as those signaling completion of an input/output (I/O) operation assigned to a device, the efficiency of processing the interrupt may vary from processor to processor. Processing efficiency and overall computer system operation may be improved by appropriately coalescing interrupt messages within and/or across a plurality of queues, where interrupts are queued on the basis of which processor they target.
摘要翻译：用于多处理器计算机的中断重定向和聚合系统。设备使用通过PCI，PCI-X或PCI Express总线与存储器写入事务通信的预定义消息地址和数据有效负载中断处理器或处理器组。通过将多个中断通知组合成单个中断消息到处理器，可以提高处理效率。对于多处理器计算机上的一些中断，例如那些信令完成分配给设备的输入/输出（I / O）操作），处理器的处理效率可能随处理器而异。可以通过适当地聚合多个队列内和/或跨多个队列的中断消息来改善处理效率和整体计算机系统操作，其中中断基于他们所针对的哪个处理器进行排队。

5. 发明申请

US20130132616A1 CHARACTERIZING DEVICE PERFORMANCE BASED ON USER-PERCEIVABLE LATENCY 有权
标题翻译：基于用户可接受的延迟来表征设备性能
公开(公告)号：US20130132616A1
公开(公告)日：2013-05-23
申请号：US13299189
申请日：2011-11-17
申请人： Bruce L. Worthington , Jason Carl Hendrickson , Robert P. Fitzgerald , Stuart Sechrest , Changjiu Xian , Qi Zhang
发明人： Bruce L. Worthington , Jason Carl Hendrickson , Robert P. Fitzgerald , Stuart Sechrest , Changjiu Xian , Qi Zhang
IPC分类号： G06F3/00
CPC分类号： G06F11/3428 , G06F11/3419 , G06F11/3485 , G06F2201/81
摘要： A method and an apparatus for characterizing performance of a device based on user-perceivable latency. To characterize device performance, a value of a metric may be computed from latencies of operations performed by the device. In computing a value of a metric, latencies may be treated differently, such that some latencies perceivable by a user of the device may have a greater impact on the value of the metric than other latencies that either are not perceivable or are perceived by the user to a lesser degree. Such a performance metric based on user-perceivable latency facilitates identification of computing device that provide a desirable user experience.
摘要翻译：一种用于基于用户可感知延迟来表征设备的性能的方法和装置。为了表征设备性能，可以根据设备执行的操作的延迟来计算度量值。在计算度量的值时，可以不同地处理延迟，使得由设备的用户感知到的某些延迟可能对度量的值具有比不可感知的或被用户感知的其他潜伏期更大的影响在较小程度上。基于用户可感知延迟的这种性能度量促进了提供期望的用户体验的计算设备的识别。

6. 发明授权

US09223675B2 Characterizing device performance based on user-perceivable latency 有权
标题翻译：基于用户可感知的延迟来表征设备性能
公开(公告)号：US09223675B2
公开(公告)日：2015-12-29
申请号：US13299189
申请日：2011-11-17
申请人： Bruce L. Worthington , Jason Carl Hendrickson , Robert P. Fitzgerald , Stuart Sechrest , Changjiu Xian , Qi Zhang
发明人： Bruce L. Worthington , Jason Carl Hendrickson , Robert P. Fitzgerald , Stuart Sechrest , Changjiu Xian , Qi Zhang
IPC分类号： G06F3/00 , G06F11/34 , G06F5/00
CPC分类号： G06F11/3428 , G06F11/3419 , G06F11/3485 , G06F2201/81
摘要： A method and an apparatus for characterizing performance of a device based on user-perceivable latency. To characterize device performance, a value of a metric may be computed from latencies of operations performed by the device. In computing a value of a metric, latencies may be treated differently, such that some latencies perceivable by a user of the device may have a greater impact on the value of the metric than other latencies that either are not perceivable or are perceived by the user to a lesser degree. Such a performance metric based on user-perceivable latency facilitates identification of computing device that provide a desirable user experience.
摘要翻译：一种用于基于用户可感知延迟来表征设备的性能的方法和装置。为了表征设备性能，可以根据设备执行的操作的延迟来计算度量值。在计算度量的值时，可以不同地处理延迟，使得由设备的用户感知到的某些延迟可能对度量的值具有比不可感知的或被用户感知的其他潜伏期更大的影响在较小程度上。基于用户可感知延迟的这种性能度量促进了提供期望的用户体验的计算设备的识别。

7. 发明授权

US09015441B2 Memory usage scanning 有权
标题翻译：内存使用扫描
公开(公告)号：US09015441B2
公开(公告)日：2015-04-21
申请号：US12770937
申请日：2010-04-30
申请人： Bruce L. Worthington , Vishal Sharda , Qi Zhang , Mehmet Iyigun , Yevgeniy Bak
发明人： Bruce L. Worthington , Vishal Sharda , Qi Zhang , Mehmet Iyigun , Yevgeniy Bak
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34 , G06F3/06 , G06F12/10 , G06F1/32 , G06F11/34
CPC分类号： G06F3/0625 , G06F1/3225 , G06F1/3268 , G06F1/3275 , G06F3/0647 , G06F3/0688 , G06F11/3471 , G06F12/1009 , G06F2201/88 , Y02D10/13 , Y02D10/14 , Y02D10/154 , Y02D10/34
摘要： A memory scanning system may scan memory objects to determine usage frequency by scanning each memory object using a mapping of the processes stored in memory. The scanning may be performed multiple times to generate a usage history for each page or unit of memory. In some cases, scanning may be performed at different frequencies to determine multiple classifications of usage. The mapping may create a detailed topology of memory usage, including multiple classifications of access frequency, as well as several other classifications. Based on the topology, the objects in memory may be copied to another storage medium or optimized for performance or power consumption.
摘要翻译：存储器扫描系统可以通过使用存储在存储器中的处理的映射扫描每个存储器对象来扫描存储器对象来确定使用频率。可以多次执行扫描以产生每个页面或存储器单元的使用历史。在某些情况下，可以以不同的频率执行扫描以确定多种使用分类。该映射可以创建存储器使用的详细拓扑，包括访问频率的多个分类以及其他几个分类。基于拓扑，内存中的对象可能被复制到另一个存储介质中，或者针对性能或功耗进行了优化。

8. 发明授权

US08479214B2 Hardware throughput saturation detection 有权
标题翻译：硬件吞吐量饱和度检测
公开(公告)号：US08479214B2
公开(公告)日：2013-07-02
申请号：US12242621
申请日：2008-09-30
申请人： Dustin L. Green , Yau Ning Chin , Bruce L. Worthington
发明人： Dustin L. Green , Yau Ning Chin , Bruce L. Worthington
IPC分类号： G06F13/00
CPC分类号： G06F9/4881
摘要： Improved hardware throughput can be achieved when a hardware device is saturated with IO jobs. Throughput can be estimated based on the quantifiable characteristics of incoming IO jobs. When IO jobs are received a time cost for each job can be estimated and stored in memory. The estimates can be used to calculate the total time cost of in-flight IO jobs and a determination can be made as to whether the hardware device is saturated based on completion times for IO jobs. Over time the time cost estimates for IO jobs can be revised based on a comparison between the estimated time cost for an IO job and the actual time cost for the IO job using aggregate IO job completion sequences.
摘要翻译：当硬件设备饱和IO作业时，可以实现改进的硬件吞吐量。吞吐量可以基于输入IO作业的可量化特征来估计。当接收到IO作业时，可以估计每个作业的时间成本并将其存储在内存中。估计值可用于计算飞行中IO作业的总时间成本，并可根据IO作业的完成时间确定硬件设备是否饱和。随着时间的推移，IO作业的时间成本估算可以根据IO作业的估计时间成本与使用汇总IO作业完成序列的IO作业的实际时间成本进行比较来修改。

9. 发明申请

US20120284543A1 USER INPUT TRIGGERED DEVICE POWER MANAGEMENT 审中-公开
标题翻译：用户输入触发的设备电源管理
公开(公告)号：US20120284543A1
公开(公告)日：2012-11-08
申请号：US13099077
申请日：2011-05-02
申请人： Changjiu Xian , Bruce L. Worthington
发明人： Changjiu Xian , Bruce L. Worthington
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/3206
摘要： Techniques for user input triggered device power management are described that enable user inputs and activities to cause selective changes in power states for a device. Power can be boosted to a high power state to improve responsiveness for designated inputs and/or activities. When responsiveness is deemed less important in connection with particular inputs and/or activities, a low power state can be set to reduce energy consumption. In at least some embodiments, selectively switching between power states includes detecting various user inputs at a device and filtering the inputs to select power states associated with the user inputs. The device can then be operated in a selected power state until a transition to a different power state is triggered by occurrence of designated events, such as running of a set time interval, further user input, and/or completion of user activity.
摘要翻译：描述用于用户输入触发的设备电源管理的技术，其使得用户输入和活动能够引起对设备的功率状态的选择性改变。电力可以提升到高功率状态，以提高对指定投入和/或活动的响应能力。当响应性被认为与特定输入和/或活动相关的重要性较低时，可以设置低功率状态以降低能量消耗。在至少一些实施例中，选择性地在功率状态之间切换包括检测设备处的各种用户输入并且过滤输入以选择与用户输入相关联的功率状态。然后可以以所选择的功率状态操作设备，直到通过发生指定事件（例如运行设定的时间间隔，进一步的用户输入和/或用户活动的完成）触发到不同功率状态的转换。

10. 发明申请

US20110145609A1 POWER AWARE MEMORY ALLOCATION 有权
标题翻译：电力记忆分配
公开(公告)号：US20110145609A1
公开(公告)日：2011-06-16
申请号：US12636732
申请日：2009-12-12
申请人： Stephen R. Berard , Sean N. McGrane , Bruce L. Worthington
发明人： Stephen R. Berard , Sean N. McGrane , Bruce L. Worthington
IPC分类号： G06F1/32 , G06F12/00 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/126
摘要： A computer system may place memory objects in specific memory physical regions based on energy consumption and performance or other policies. The system may have multiple memory regions at least some of which may be powered down or placed in a low power state during system operation. The memory object may be characterized in terms of access frequency, movability, and desired performance and placed in an appropriate memory region. In some cases, the memory object may be placed in a temporary memory region and later moved to a final memory region for long term placement. The policies may allow some processes to operate while consuming less energy, while other processes may be configured to maximize performance
摘要翻译：计算机系统可以基于能量消耗和性能或其他策略将存储器对象放置在特定存储器物理区域中。系统可以具有多个存储器区域，其中至少一些可以在系统操作期间被掉电或置于低功率状态。可以根据访问频率，可移动性和期望的性能来表征存储器对象，并将其放置在适当的存储器区域中。在一些情况下，存储器对象可以被放置在临时存储器区域中，并且随后被移动到最终存储器区域以进行长期放置。这些策略可以允许一些进程在消耗更少的能量的同时运行，而其他进程可以被配置为使性能最大化

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