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1. 发明授权

US07475303B1 HyperJTAG system including debug probe, on-chip instrumentation, and protocol 有权
标题翻译： HyperJTAG系统包括调试探针，片上仪器和协议
公开(公告)号：US07475303B1
公开(公告)日：2009-01-06
申请号：US11026324
申请日：2004-12-29
申请人： Ernest Lewis Edgar , Bruce J. Ableidinger
发明人： Ernest Lewis Edgar , Bruce J. Ableidinger
IPC分类号： G01R31/28 , G01R31/08 , G06F11/00
CPC分类号： G01R31/31907 , G06F11/2236
摘要： A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip instrumentation includes an on-chip instrumentation concentrator and an on-chip instrumentation de-concentrator. The probe includes a probe concentrator and a probe de-concentrator. The probe concentrator concentrates signals from the test instruments into a first serial signal stream for transmission over the connector mechanism. The on-chip instrumentation de-concentrator de-concentrates the first serial signal stream into signals to be directed to at least one of the processor cores. The on-chip instrumentation concentrator concentrates signals from the processor cores into a second serial signal stream for transmission over the connector mechanism. The probe de-concentrator de-concentrates the second serial signal stream into signals to be directed to at least one of the testing instruments. Using this system, the testing instruments are able to simultaneously access and control respective processor cores. In one preferred embodiment the plurality of signals are directed to the processor cores using a plurality of loops, each loop having a chain of nodes, each of the processor cores connected to a respective node.
摘要翻译：用于同时将多个测试仪器与多个处理器核心连接的系统包括片上仪器，探针和连接机构，用于在探针和片上仪器之间提供传输路径。片上仪器包括片上仪表集中器和片上仪表集中器。探头包括探针集中器和探头去集中器。探头集中器将来自测试仪器的信号集中到第一串行信号流中，以在连接器机构上传输。片上仪表去集中器将第一串行信号流集中到要被指向至少一个处理器核的信号中。片上仪器集中器将来自处理器核心的信号集中到第二串行信号流中，以在连接器机构上传输。探头去集中器将第二串行信号流集中到要被引导到至少一个测试仪器的信号中。使用该系统，测试仪器能够同时访问和控制相应的处理器内核。在一个优选实施例中，使用多个环路将多个信号引导到处理器核心，每个环路具有一个节点链，每个处理器核心连接到相应的节点。

2. 发明授权

US07613966B2 Hyperjtag system including debug probe, on-chip instrumentation, and protocol 有权
标题翻译： Hyperjtag系统包括调试探针，片上仪器和协议
公开(公告)号：US07613966B2
公开(公告)日：2009-11-03
申请号：US12348847
申请日：2009-01-05
申请人： Ernest Lewis Edgar , Bruce J. Ableidinger
发明人： Ernest Lewis Edgar , Bruce J. Ableidinger
IPC分类号： G01R31/28
CPC分类号： G01R31/31907 , G06F11/2236
摘要： A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip instrumentation includes an on-chip instrumentation concentrator and an on-chip instrumentation de-concentrator. The probe includes a probe concentrator and a probe de-concentrator. The probe concentrator concentrates signals from the test instruments into a first serial signal stream for transmission over the connector mechanism. The on-chip instrumentation de-concentrator de-concentrates the first serial signal stream into signals to be directed to at least one of the processor cores. The on-chip instrumentation concentrator concentrates signals from the processor cores into a second serial signal stream for transmission over the connector mechanism. The probe de-concentrator de-concentrates the second serial signal stream into signals to be directed to at least one of the testing instruments. Using this system, the testing instruments are able to simultaneously access and control respective processor cores. In one preferred embodiment the plurality of signals are directed to the processor cores using a plurality of loops, each loop having a chain of nodes, each of the processor cores connected to a respective node.
摘要翻译：用于同时将多个测试仪器与多个处理器核心连接的系统包括片上仪器，探针和连接机构，用于在探针和片上仪器之间提供传输路径。片上仪器包括片上仪表集中器和片上仪表集中器。探头包括探针集中器和探头去集中器。探头集中器将来自测试仪器的信号集中到第一串行信号流中，以在连接器机构上传输。片上仪表去集中器将第一串行信号流集中到要被指向至少一个处理器核的信号中。片上仪器集中器将来自处理器核心的信号集中到第二串行信号流中，以在连接器机构上传输。探头去集中器将第二串行信号流集中到要被引导到至少一个测试仪器的信号中。使用该系统，测试仪器能够同时访问和控制相应的处理器内核。在一个优选实施例中，使用多个环路将多个信号引导到处理器核心，每个环路具有一个节点链，每个处理器核心连接到相应的节点。

3. 发明申请

US20110016289A1 Apparatus and Method for Profiling Software Performance on a Processor with Non-Unique Virtual Addresses 有权
标题翻译：在具有非唯一虚拟地址的处理器上分析软件性能的装置和方法
公开(公告)号：US20110016289A1
公开(公告)日：2011-01-20
申请号：US12506153
申请日：2009-07-20
申请人： Bruce J. Ableidinger
发明人： Bruce J. Ableidinger
IPC分类号： G06F12/10 , G06F12/00 , G06F11/07
CPC分类号： G06F11/3471 , G06F2201/865 , G06F2201/88
摘要： A system includes a processor with a memory map specifying a user mode region with virtual address translation by a memory management unit and a kernel mode region with direct virtual address translation. The processor executes an application in the user mode region where virtual addresses are not unique. A probe receives trace information from the processor. A host system receives the trace information from the probe. The host system includes a data structure associating a process name, a process identification and a set of instruction counters. Each instruction counter is incremented upon the processing of a designated virtual address within the trace information. A profiling module processes information associated with the process name and set of instruction counters to identify a performance problem in the application.
摘要翻译：系统包括处理器，其具有指定由存储器管理单元进行虚拟地址转换的用户模式区域的存储器映射和具有直接虚拟地址转换的内核模式区域。处理器在虚拟地址不唯一的用户模式区域中执行应用程序。探测器从处理器接收跟踪信息。主机系统从探测器接收跟踪信息。主机系统包括将进程名称，进程标识和一组指令计数器相关联的数据结构。每个指令计数器在跟踪信息中处理指定的虚拟地址时递增。分析模块处理与进程名称和指令计数器集相关联的信息，以识别应用程序中的性能问题。

4. 发明授权

US4937740A Real time software analyzing system for storing selective m-bit addresses based upon correspondingly generated n-bit tags 失效
标题翻译：用于基于相应生成的n位标签来存储选择性m位地址的实时软件分析系统
公开(公告)号：US4937740A
公开(公告)日：1990-06-26
申请号：US161284
申请日：1988-02-29
申请人： Nirmal K. Agarwal , Bruce J. Ableidinger
发明人： Nirmal K. Agarwal , Bruce J. Ableidinger
IPC分类号： G06F11/34 , G06F11/36
CPC分类号： G06F11/3636 , G06F11/348 , G06F11/3648
摘要： A software analysis system for acquiring, storing, and analyzing certain predetermined characteristics of a computer program includes a method and apparatus for acquiring certain lines of high-level language instruction code without the need for statistical sampling. Each line of instruction code generates at least one address in assembly language which is encoded with a tag and stored in a first-in, first-out memory. The memory output is asynchronous with its output such that tagged addresses are stored in real time but extracted from memory at a predetermined rate. This allows the system to acquire all software event of interest. Each tagged address is also marked with a time stamp so that the time between acquisition of each of the software events of interest may be analyzed to determine, for example, the length of time spent in a particular subroutine.
摘要翻译：用于获取，存储和分析计算机程序的某些预定特性的软件分析系统包括用于在不需要统计抽样的情况下获取某些高级语言指令代码行的方法和装置。每行指令代码以汇编语言生成至少一个地址，该地址以标签编码并存储在先入先出的存储器中。存储器输出与其输出异步，使得标记的地址被实时存储，但是以预定的速率从存储器提取。这允许系统获取所有感兴趣的软件事件。每个标记的地址还标记有时间戳，以便可以分析获取感兴趣的每个软件事件之间的时间，以确定例如在特定子程序中花费的时间长度。

5. 发明授权

US08185717B2 Apparatus and method for profiling software performance on a processor with non-unique virtual addresses 有权
标题翻译：在具有非唯一虚拟地址的处理器上分析软件性能的装置和方法
公开(公告)号：US08185717B2
公开(公告)日：2012-05-22
申请号：US12506153
申请日：2009-07-20
申请人： Bruce J. Ableidinger
发明人： Bruce J. Ableidinger
IPC分类号： G06F12/08
CPC分类号： G06F11/3471 , G06F2201/865 , G06F2201/88
摘要： A system includes a processor with a memory map specifying a user mode region with virtual address translation by a memory management unit and a kernel mode region with direct virtual address translation. The processor executes an application in the user mode region where virtual addresses are not unique. A probe receives trace information from the processor. A host system receives the trace information from the probe. The host system includes a data structure associating a process name, a process identification and a set of instruction counters. Each instruction counter is incremented upon the processing of a designated virtual address within the trace information. A profiling module processes information associated with the process name and set of instruction counters to identify a performance problem in the application.
摘要翻译：系统包括处理器，其具有指定由存储器管理单元进行虚拟地址转换的用户模式区域的存储器映射和具有直接虚拟地址转换的内核模式区域。处理器在虚拟地址不唯一的用户模式区域中执行应用程序。探测器从处理器接收跟踪信息。主机系统从探测器接收跟踪信息。主机系统包括将进程名称，进程标识和一组指令计数器相关联的数据结构。每个指令计数器在跟踪信息中处理指定的虚拟地址时递增。分析模块处理与进程名称和指令计数器集相关联的信息，以识别应用程序中的性能问题。

6. 发明申请

US20090119555A1 Hyperjtag System Including Debug Probe, On-Chip Instrumentation, and Protocol 有权
标题翻译： Hyperjtag系统包括调试探针，片上仪器和协议
公开(公告)号：US20090119555A1
公开(公告)日：2009-05-07
申请号：US12348847
申请日：2009-01-05
申请人： Ernest Lewis Edgar , Bruce J. Ableidinger
发明人： Ernest Lewis Edgar , Bruce J. Ableidinger
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31907 , G06F11/2236
摘要： A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip instrumentation includes an on-chip instrumentation concentrator and an on-chip instrumentation de-concentrator. The probe includes a probe concentrator and a probe de-concentrator. The probe concentrator concentrates signals from the test instruments into a first serial signal stream for transmission over the connector mechanism. The on-chip instrumentation de-concentrator de-concentrates the first serial signal stream into signals to be directed to at least one of the processor cores. The on-chip instrumentation concentrator concentrates signals from the processor cores into a second serial signal stream for transmission over the connector mechanism. The probe de-concentrator de-concentrates the second serial signal stream into signals to be directed to at least one of the testing instruments. Using this system, the testing instruments are able to simultaneously access and control respective processor cores. In one preferred embodiment the plurality of signals are directed to the processor cores using a plurality of loops, each loop having a chain of nodes, each of the processor cores connected to a respective node.
摘要翻译：用于同时将多个测试仪器与多个处理器核心连接的系统包括片上仪器，探针和连接机构，用于在探针和片上仪器之间提供传输路径。片上仪器包括片上仪表集中器和片上仪表集中器。探头包括探针集中器和探头去集中器。探头集中器将来自测试仪器的信号集中到第一串行信号流中，以在连接器机构上传输。片上仪表去集中器将第一串行信号流集中到要被指向至少一个处理器核的信号中。片上仪器集中器将来自处理器核心的信号集中到第二串行信号流中，以在连接器机构上传输。探头去集中器将第二串行信号流集中到要被引导到至少一个测试仪器的信号中。使用该系统，测试仪器能够同时访问和控制相应的处理器内核。在一个优选实施例中，使用多个环路将多个信号引导到处理器核心，每个环路具有一个节点链，每个处理器核心连接到相应的节点。

7. 发明授权

US4513395A Apparatus and method for acquiring multiple groups of data signals from a synchronous logic system 失效
标题翻译：用于从同步逻辑系统获取多组数据信号的装置和方法
公开(公告)号：US4513395A
公开(公告)日：1985-04-23
申请号：US479089
申请日：1983-03-25
申请人： Michael D. Henry , Bruce J. Ableidinger , Nirmal K. Agarwal
发明人： Michael D. Henry , Bruce J. Ableidinger , Nirmal K. Agarwal
IPC分类号： G01R31/3177 , G06F5/10 , G06F11/25 , G06F1/00
CPC分类号： G06F5/10 , G01R31/3177 , G06F11/25 , G06F2205/106
摘要： An apparatus and method which may be used with a logic analyzer are provided for acquiring groups of data words from the circuitry of a synchronous logic system where each group contains a qualified data word together with a predetermined number of data words which have preceded it. The apparatus includes a circuit for detecting the qualified word and a data storage device having a plurality of separately-addressable storage locations. Both the qualified data detector and the storage device are logically connected to the synchronous logic circuitry. The apparatus further includes an addressing circuit which responds to the detection of a qualified word and to the presence of data words on the synchronous logic circuitry by producing storage addresses which are provided to the storage device for storing the data word groups in successive storage locations. In an alternative embodiment, the addressing means responds to qualified word detection and to the number of data words stored in the storage locations such that each stored group of data words contains a qualified word and a respective number of data words.
摘要翻译：提供了可以与逻辑分析器一起使用的装置和方法，用于从同步逻辑系统的电路中获取数据字组，其中每个组包含限定数据字以及其之前的预定数量的数据字。该装置包括用于检测合格字的电路和具有多个可单独寻址的存储位置的数据存储装置。合格数据检测器和存储设备都逻辑连接到同步逻辑电路。该装置还包括寻址电路，其通过产生提供给存储装置的用于在连续存储位置中存储数据字组的存储地址来响应对合格字的检测和数据字的存在。在替代实施例中，寻址装置响应于合格的字检测和存储在存储位置中的数据字的数量，使得每个存储的数据字组包含合格字和相应数量的数据字。

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