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1. 发明授权

US5418935A Apparatus for preventing double drive occurrences on a common bus by delaying enablement of one driver after indication of disablement to other driver is received 失效
标题翻译：接收到在向其他驾驶员指示禁用指示之后通过延迟启动一个驾驶员来在公共总线上预防双重驱动事件的装置
公开(公告)号：US5418935A
公开(公告)日：1995-05-23
申请号：US167583
申请日：1993-12-14
申请人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
发明人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
IPC分类号： G06F13/14 , G06F13/40 , G06F13/10 , G06F13/36
CPC分类号： G06F13/14 , G06F13/4077
摘要： In a digital data transfer system whereby a plurality of driver units are all connected to and share the same common system bus, there is provided control gating logic which will prevent the enablement of a subsequent driver for a fixed delay time until it is certain that the previous driver has been shut down. Due to switching time variations in driving units, a fixed delay time is set to function in a first driver that is beginning its data transmission to be sure that another driver which was previously transmitting data has been completely turned-off before the first driver gains access to the commonly shared bus. This ensures that no two drivers can simultaneously be driving data onto the system bus at the same time which would obviate the integrity of data transmitted.
摘要翻译：在数字数据传输系统中，多个驱动器单元都连接到并共享相同的公共系统总线，提供了控制门控逻辑，其将阻止后续驱动器实现固定的延迟时间，直到确定以前的司机已被关闭。由于驱动单元的切换时间变化，固定的延迟时间被设置为在正在开始其数据传输的第一驱动器中起作用，以确保在第一驱动器获得访问之前先前发送数据的另一驱动器已经完全关闭到共享公共汽车。这确保没有两个驱动程序可以同时将数据驱动到系统总线上，这将消除传输的数据的完整性。

2. 发明授权

US5321814A System for optional module detection and reconfiguration 失效
标题翻译：可选模块检测和重新配置的系统
公开(公告)号：US5321814A
公开(公告)日：1994-06-14
申请号：US897610
申请日：1992-06-10
申请人： Saul Barajas , Leland E. Watson , Bruce E. Whittaker
发明人： Saul Barajas , Leland E. Watson , Bruce E. Whittaker
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4072
摘要： An automatic re-configurable computer system having a standard processor module and standard main memory and I/O control modules where each module is inter-connected to a common system bus. Automatic re-configuration occurs in the standard modules, when an optional module is connected onto the system bus, permitting inter-cooperation between the standard and optional modules to take place.
摘要翻译：一种具有标准处理器模块和标准主存储器和I / O控制模块的自动重新配置的计算机系统，其中每个模块与公共系统总线相互连接。自动重新配置发生在标准模块中，当可选模块连接到系统总线上时，允许标准模块和可选模块之间进行互操作。

3. 发明授权

US5117132A Flexible utilization of general flip-flops in programmable array logic 失效
标题翻译：一般触发器在可编程阵列逻辑中的灵活应用
公开(公告)号：US5117132A
公开(公告)日：1992-05-26
申请号：US652847
申请日：1991-02-08
申请人： Leland E. Watson , Saul Barajas , Bruce E. Whittaker
发明人： Leland E. Watson , Saul Barajas , Bruce E. Whittaker
IPC分类号： H03K19/177
CPC分类号： H03K19/17708
摘要： A programmable array logic unit (PAL) having a disconnected array of gates, inverters and D-Type flip-flops, is utilized by burning-in the interconnections, to enable the D flip-flops to function as J-K flip-flops and/or toggle flip-flops to enable flexibility in the functions available for utilization, by providing inputs for Direct Set, Direct Clear and Hold.
摘要翻译：具有断开的门阵列，反相器和D型触发器的可编程阵列逻辑单元（PAL）通过在互连中燃烧而被利用，以使D触发器用作JK触发器和/或通过提供直接设置，直接清除和保持的输入，可切换触发器以实现可用功能的灵活性。

4. 发明授权

US5086427A Clocked logic circuitry preventing double driving on shared data bus 失效
标题翻译：时钟逻辑电路防止共享数据总线上的双重驱动
公开(公告)号：US5086427A
公开(公告)日：1992-02-04
申请号：US506392
申请日：1990-04-09
申请人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
发明人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
IPC分类号： H04J3/04 , H04L12/40
CPC分类号： H04J3/047
摘要： A system wherein multiple sources of data each have drivers for transmitting data to a common system bus. The drivers are each managed by individual enabling logic which is controlled by a flip-flop driven by a clock. Thus no driver can connect and drive data onto the bus until one clock period after the previously connected driver has been disabled and disconnected from the bus.
摘要翻译：一种系统，其中多个数据源具有用于将数据发送到公共系统总线的驱动器。驱动器各自由单个使能逻辑管理，该逻辑由时钟驱动的触发器控制。因此，在先前连接的驱动程序已被禁用并与总线断开连接之前，没有驱动程序可以连接和驱动数据到总线上。

5. 发明授权

US5459836A Inter-processor communication net 失效
标题翻译：处理器间通信网
公开(公告)号：US5459836A
公开(公告)日：1995-10-17
申请号：US970536
申请日：1992-11-02
申请人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
发明人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
IPC分类号： G06F15/167 , G06F3/00 , G06F15/16
CPC分类号： G06F15/167
摘要： A message transfer system between multiple processors in a network. Each processor includes an interprocessor communications (IPC) hardware unit having an unique address count. An address count generator in a designated IPC hardware unit generates a sequence of binary count numbers such that when the generated count number matches the address of the IPC hardware unit, then that particular hardware unit and its associated processor are granted a time period of bus access for sending messages on the IPC network bus to other processors. Messages on the IPC network bus can be received by an IPC hardware unit at any time irrespective of the generated count number. Any sending processor that has bus access can concurrently provide multiple messages where each of the multiple messages is directed to each particular processor for reception. Thus one sender, with bus access, can communicate with multiple receivers during its transmission onto the IPC network bus connecting the processors.
摘要翻译：网络中多个处理器之间的消息传输系统。每个处理器包括具有唯一地址计数的处理器间通信（IPC）硬件单元。在指定的IPC硬件单元中的地址计数发生器产生二进制计数号序列，使得当生成的计数号与IPC硬件单元的地址匹配时，那个特定硬件单元及其相关处理器被授予总线访问时间段用于将IPC网络总线上的消息发送到其他处理器。 IPC网络总线上的消息可以由IPC硬件单元随时接收，而与生成的计数号无关。具有总线访问权的任何发送处理器可同时提供多个消息，其中多个消息中的每一个被定向到每个特定处理器用于接收。因此，一个具有总线访问权限的发送者可以在多个接收器传输到连接处理器的IPC网络总线上进行通信。

6. 发明授权

US5146596A Multiprocessor multifunction arbitration system with two levels of bus access including priority and normal requests 失效
标题翻译：具有两级总线访问的多处理器多功能仲裁系统，包括优先级和正常请求
公开(公告)号：US5146596A
公开(公告)日：1992-09-08
申请号：US471904
申请日：1990-01-29
申请人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
发明人： Bruce E. Whittaker , Saul Barajas , Leland E. Watson
IPC分类号： G06F13/364
CPC分类号： G06F13/364
摘要： Arbitration and control circuitry for monitoring the two processors sharing a system bus to insure fair access to system resources and to sense error conditions which occur in order to hold access for the processor involved until the error condition is cleared. The arbitration circuitry provides for two levels of bus access requests where one level involves normal requests and a second level involves priority request which take precedence over normal requests.
摘要翻译：用于监视共享系统总线的两个处理器的仲裁和控制电路，以确保公平地访问系统资源，并感测发生的错误状况，以便保持所涉及的处理器的访问，直到错误状况被清除。仲裁电路提供两级总线访问请求，其中一级涉及正常请求，而第二级涉及优先于正常请求的优先级请求。

7. 发明授权

US5506967A Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures 失效
标题翻译：高速缓存无效化系统在缓存定向计算机体系结构中具有可调节级别阈值的存储队列
公开(公告)号：US5506967A
公开(公告)日：1996-04-09
申请号：US78361
申请日：1993-06-15
申请人： Saul Barajas , David M. Kalish , Bruce E. Whittaker
发明人： Saul Barajas , David M. Kalish , Bruce E. Whittaker
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0808 , G06F12/0831
摘要： In a time-shared bus computer system with processors having cache memories, an adjustable invalidation queue for use in the cache memories. The invalidation queue has adjustable upper and lower limit positions that define when the queue is logically full and logically empty, respectively. The queue is flushed down to the lower limit when the contents of the queue attain the upper limit. During the queue flushing operation, WRITE requests on the bus are RETRYed. The computer maintenance system sets the upper and lower limits at system initialization time to optimize system performance under maximum bus traffic conditions.
摘要翻译：在具有处理器的具有高速缓存存储器的时分共享总线计算机系统中，可用于高速缓冲存储器的可调节无效队列。无效队列具有可调节的上限和下限位置，可以分别定义队列在逻辑上完全和逻辑上为空。当队列的内容达到上限时，队列被刷新到下限。在队列刷新操作期间，总线上的WRITE请求被复原。计算机维护系统在系统初始化时间设置上限和下限，以在最大总线流量条件下优化系统性能。

8. 发明授权

US6070166A Apparatus and method for compressing a plurality of contiguous addresses to form a compressed block address using the first address of the contiguous addresses and a block identifier bit 失效
标题翻译：用于使用连续地址的第一地址和块标识符比特来压缩多个相邻地址以形成压缩块地址的装置和方法
公开(公告)号：US6070166A
公开(公告)日：2000-05-30
申请号：US999857
申请日：1997-06-10
申请人： Bruce E. Whittaker , Donald M. Kalish , Saul Barajas
发明人： Bruce E. Whittaker , Donald M. Kalish , Saul Barajas
IPC分类号： G06F12/08 , G06F7/00
CPC分类号： G06F12/0808 , G06F12/0831 , Y10S707/99942
摘要： A method for compressing a plurality of contiguous addresses for storage in a queue. The method includes recognizing that a first address of the plurality of addresses is an individual address that corresponds to a memory location that is transferred individually. A first value of a block identifier bit is associated with the first address, with the first value identifying the first address as an individual address. The first address and the first value of the block identifier bit are stored into the queue. A further address of the plurality of addresses is recognized as a block address corresponding to a plurality of contiguous data words that reside at a respective plurality of contiguous addresses, that begin with the further address, and that are transferred as a block unit. A second value of the block identifier bit is associated with the further address, the second value identifying the further address as a block address. The second value of the block identifier bit and only the further address of the plurality of contiguous addresses are stored into the queue, thereby compressing the plurality of addresses stored in the queue.
摘要翻译：一种用于压缩多个连续地址以存储在队列中的方法。该方法包括识别多个地址的第一地址是对应于单独传送的存储器位置的单独地址。块标识符位的第一值与第一地址相关联，第一个值将第一地址标识为单独的地址。块标识符位的第一个地址和第一个值被存储到队列中。多个地址的另一地址被识别为对应于驻留在相应多个相邻地址的多个相邻数据字的块地址，其以另一地址开始，并以块为单位传送。块标识符位的第二值与另外的地址相关联，第二值将其它地址标识为块地址。块标识符位的第二值和仅多个连续地址的另外的地址被存储到队列中，从而压缩存储在队列中的多个地址。

9. 发明授权

US5561773A Programmable, multi-purpose virtual pin multiplier 失效
标题翻译：可编程，多用途虚拟引脚倍增器
公开(公告)号：US5561773A
公开(公告)日：1996-10-01
申请号：US56324
申请日：1993-04-30
申请人： David M. Kalish , Saul Barajas , Bruce E. Whittaker
发明人： David M. Kalish , Saul Barajas , Bruce E. Whittaker
IPC分类号： H03K19/173 , G06F11/00 , G06F7/38 , H01J3/00
CPC分类号： H03K19/1732
摘要： A system and circuitry is provided by which certain selected embedded pins of an integrated circuit gate array may be provided with dual functions, that is to say, they may act either as receivers of an externally sourced input signal or as transmitters of an internally generated output signal. Each selected input/output pin is controlled by an associated flip-flop residing in a chain of flip-flops so that an associated flip-flop will determine the condition of two buffer-drivers attached to each input/output pin. While the first buffer-driver is tri-stated (disabled), then the embedded pin operates as an input receiving function. When the first buffer-driver is enabled, the embedded I/O pin operates as the conveyer of an output signal from the internal output logic.
摘要翻译：提供了一种系统和电路，通过该系统和电路可以提供集成电路门阵列的某些选定的嵌入式引脚具有双重功能，也就是说，它们可以作为外部来源输入信号的接收器，或作为内部产生的输出的发射器信号。每个选择的输入/输出引脚由驻留在触发器链中的相关联的触发器控制，使得相关联的触发器将确定连接到每个输入/输出引脚的两个缓冲器驱动器的状况。当第一个缓冲驱动器为三态（禁用）时，嵌入式引脚作为输入接收功能。当第一个缓冲驱动器被使能时，嵌入式I / O引脚作为来自内部输出逻辑的输出信号的输送器。

10. 发明授权

US5642486A Invalidation queue with "bit-sliceability" 失效
标题翻译：无效队列具有“位切换性”
公开(公告)号：US5642486A
公开(公告)日：1997-06-24
申请号：US92433
申请日：1993-07-15
申请人： Bruce E. Whittaker , David M. Kalish , Saul Barajas
发明人： Bruce E. Whittaker , David M. Kalish , Saul Barajas
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0831 , Y10S707/99942
摘要： An Invalidation Queue (IQ) arrangement in a computer system having Main Memory and, Cache-Memory, with a pair of intermediate main-buses this IQ arrangement comprising: a pair of split IQ ASIC Arrays disposed between each Cache-Memory and the main-buses and being adapted to assure identical data in all identical memory addresses in different caches, and to "remember" write-operations along the buses and to execute invalidation sequences for any Cache-Memory unit as dictated by that Cache-Memory unit.
摘要翻译：具有主存储器的计算机系统中的无效队列（IQ）布置，以及具有一对中间主总线的高速缓存存储器，该IQ布置包括：设置在每个高速缓存存储器和主存储器之间的一对分离IQ ASIC阵列，总线，并且适于确保不同高速缓存中的所有相同存储器地址中的相同数据，并且沿着总线“记住”写入操作，并且执行由该高速缓存存储器单元所指示的任何高速缓存存储器单元的无效序列。

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