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1. 发明授权

US08383483B2 High performance CMOS circuits, and methods for fabricating same 有权
标题翻译：高性能CMOS电路及其制造方法
公开(公告)号：US08383483B2
公开(公告)日：2013-02-26
申请号：US12541562
申请日：2009-08-14
申请人： John C. Arnold , Glenn A. Biery , Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Michael A. Gribelyuk , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Joseph S. Newbury , Vamsi K. Paruchuri , Michelle L. Steen
发明人： John C. Arnold , Glenn A. Biery , Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Michael A. Gribelyuk , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Joseph S. Newbury , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L21/336
CPC分类号： H01L21/823857 , H01L21/823842
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路，其各自包含至少第一和第二栅极堆叠。第一栅极堆叠位于半导体衬底中的第一器件区域（例如，n-FET器件区域）上，并且至少从底部至顶部包括栅极介电层，金属栅极导体和含硅的门导体。第二栅极堆叠位于半导体衬底中的第二器件区域（例如，p-FET器件区域）上，并且至少包括从栅极电介质层和含硅栅极导体的底部到顶部。可以通过本发明的各种方法以集成的方式在半导体衬底上形成第一和第二栅极叠层。

2. 发明授权

US07999323B2 Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices 有权
标题翻译：使用金属/金属氮化物双层作为自对准积极缩放的CMOS器件中的栅电极
公开(公告)号：US07999323B2
公开(公告)日：2011-08-16
申请号：US12542087
申请日：2009-08-17
申请人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
发明人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
IPC分类号： H01L29/00
CPC分类号： H01L21/823842
摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
摘要翻译：本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。本发明还提供了制造这种CMOS结构的方法。

3. 发明授权

US07709902B2 Metal gate CMOS with at least a single gate metal and dual gate dielectrics 有权
标题翻译：具有至少一个栅极金属和双栅极电介质的金属栅极CMOS
公开(公告)号：US07709902B2
公开(公告)日：2010-05-04
申请号：US12211647
申请日：2008-09-16
申请人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L31/119
CPC分类号： H01L21/823857 , H01L21/823878 , H01L21/84
摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.
摘要翻译：提供了包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET的互补金属氧化物半导体（CMOS）结构。根据本发明，nFET和pFET都包括至少一个栅极金属，并且nFET栅极堆叠被设计成具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质堆没有净正电荷。特别地，本发明提供了一种CMOS结构，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。在本发明的一个实施例中，第一栅极电介质堆叠包括第一高k电介质和含碱土金属的层或含稀土金属的层，而第二高k栅介质叠层包括第二高k电介质。

4. 发明申请

US20090011552A1 METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS 有权
标题翻译：金属门CMOS至少具有单栅极金属和双栅电极
公开(公告)号：US20090011552A1
公开(公告)日：2009-01-08
申请号：US12210703
申请日：2008-09-15
申请人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823878 , H01L21/84
摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.
摘要翻译：提供了包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET的互补金属氧化物半导体（CMOS）结构。根据本发明，nFET和pFET都包括至少单个栅极金属，并且nFET栅极堆叠被设计为具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质堆没有净正电荷。特别地，本发明提供了一种CMOS结构，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。在本发明的一个实施例中，第一栅极电介质堆叠包括第一高k电介质和含碱土金属的层或含稀土金属的层，而第二高k栅介质叠层包括第二高k电介质。

5. 发明授权

US08569844B2 Metal gate CMOS with at least a single gate metal and dual gate dielectrics 有权
标题翻译：具有至少一个栅极金属和双栅极电介质的金属栅极CMOS
公开(公告)号：US08569844B2
公开(公告)日：2013-10-29
申请号：US12211649
申请日：2008-09-16
申请人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L31/119
CPC分类号： H01L21/823857 , H01L21/823878 , H01L21/84
摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.
摘要翻译：提供了包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET的互补金属氧化物半导体（CMOS）结构。根据本发明，nFET和pFET都包括至少单个栅极金属，并且nFET栅极堆叠被设计为具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质堆没有净正电荷。特别地，本发明提供了一种CMOS结构，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。在本发明的一个实施例中，第一栅极电介质堆叠包括第一高k电介质和含碱土金属的层或含稀土金属的层，而第二高k栅介质叠层包括第二高k电介质。

6. 发明申请

US20100041221A1 HIGH PERFORMANCE CMOS CIRCUITS, AND METHODS FOR FABRICATING SAME 有权
标题翻译：高性能CMOS电路及其制造方法
公开(公告)号：US20100041221A1
公开(公告)日：2010-02-18
申请号：US12541562
申请日：2009-08-14
申请人： John C. Arnold , Glenn A. Biery , Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Michael A. Gribelyuk , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Joseph S. Newbury , Vamsi K. Paruchuri , Michelle L. Steen
发明人： John C. Arnold , Glenn A. Biery , Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Michael A. Gribelyuk , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Joseph S. Newbury , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L21/28
CPC分类号： H01L21/823857 , H01L21/823842
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路，其各自包含至少第一和第二栅极堆叠。第一栅极堆叠位于半导体衬底中的第一器件区域（例如，n-FET器件区域）上，并且至少从底部至顶部包括栅极介电层，金属栅极导体和含硅的门导体。第二栅极堆叠位于半导体衬底中的第二器件区域（例如，p-FET器件区域）上，并且至少包括从栅极电介质层和含硅栅极导体的底部到顶部。可以通过本发明的各种方法以集成的方式在半导体衬底上形成第一和第二栅极叠层。

7. 发明申请

US20090302399A1 Using Metal/Metal Nitride Bilayers as Gate Electrodes in Self-Aligned Aggressively Scaled CMOS Devices 有权
标题翻译：使用金属/金属氮化物二层作为自对准激光缩放CMOS器件中的栅极电极
公开(公告)号：US20090302399A1
公开(公告)日：2009-12-10
申请号：US12542087
申请日：2009-08-17
申请人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
发明人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
IPC分类号： H01L29/78
CPC分类号： H01L21/823842
摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
摘要翻译：本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。本发明还提供了制造这种CMOS结构的方法。

8. 发明授权

US07666732B2 Method of fabricating a metal gate CMOS with at least a single gate metal and dual gate dielectrics 有权
标题翻译：用至少单个栅极金属和双栅极电介质制造金属栅极CMOS的方法
公开(公告)号：US07666732B2
公开(公告)日：2010-02-23
申请号：US12210703
申请日：2008-09-15
申请人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823878 , H01L21/84
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a method of fabricating a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction.
摘要翻译：提供一种制造互补金属氧化物半导体（CMOS）结构的方法，其包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET。根据本发明，nFET和pFET都包括至少一个栅极金属，并且nFET栅极堆叠被设计成具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质堆没有净正电荷。特别地，本发明提供了一种制造CMOS结构的方法，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。

9. 发明授权

US07598545B2 Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices 有权
标题翻译：使用金属/金属氮化物双层作为自对准积极缩放的CMOS器件中的栅电极
公开(公告)号：US07598545B2
公开(公告)日：2009-10-06
申请号：US11111592
申请日：2005-04-21
申请人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
发明人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
IPC分类号： H01L29/00
CPC分类号： H01L21/823842
摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
摘要翻译：本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。本发明还提供了制造这种CMOS结构的方法。

10. 发明申请

US20090008720A1 METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS 有权
公开(公告)号：US20090008720A1
公开(公告)日：2009-01-08
申请号：US12211649
申请日：2008-09-16
申请人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L29/423 , H01L27/092
CPC分类号： H01L21/823857 , H01L21/823878 , H01L21/84
摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.

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