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1. 发明授权

US07642958B2 Satellite positioning system receivers and methods 有权
标题翻译：卫星定位系统接收机和方法
公开(公告)号：US07642958B2
公开(公告)日：2010-01-05
申请号：US11158127
申请日：2005-06-21
申请人： Bruce A. Bernhardt , William P. De Clerck , Michael W. Schellinger
发明人： Bruce A. Bernhardt , William P. De Clerck , Michael W. Schellinger
IPC分类号： G01S1/00 , G01C21/30 , H04W24/00
CPC分类号： G01S19/34 , G01S19/254 , G01S19/256 , G01S19/258
摘要： A mobile wireless communication device (200) including a wireless transceiver (210) communicably coupled to a processor (220), a satellite positioning system receiver (250), wherein the processor controls an operating mode of the satellite positioning system receiver based on satellite positioning system operating mode information received by the wireless transceiver when the mobile wireless communication device is in a vicinity of a location or will be in the vicinity on which the satellite positioning system operating mode information is based. Controlling the operating mode includes controller whether and when and the frequency with which location measurements are made.
摘要翻译：一种移动无线通信设备（200），包括可通信地耦合到处理器（220）的无线收发器（210），卫星定位系统接收器（250），其中处理器基于卫星定位来控制卫星定位系统接收机的操作模式当移动无线通信设备处于某个位置附近或将在卫星定位系统操作模式信息所基于的附近时由无线收发器接收的系统操作模式信息。控制操作模式包括控制器是否和何时以及进行位置测量的频率。

2. 发明授权

US5641712A Method and structure for reducing capacitance between interconnect lines 失效
标题翻译：降低互连线间电容的方法和结构
公开(公告)号：US5641712A
公开(公告)日：1997-06-24
申请号：US512253
申请日：1995-08-07
申请人： Gordon M. Grivna , Karl J. Johnson , Bruce A. Bernhardt
发明人： Gordon M. Grivna , Karl J. Johnson , Bruce A. Bernhardt
IPC分类号： H01L21/768 , H01L23/522 , H01L21/28
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002
摘要： A method and structure for reducing capacitance between interconnect lines (11, 24, 26) utilizes air gaps (17, 47) between the interconnect lines (11, 24, 26). Deposited over the interconnect lines (11, 24, 26), a silane oxide layer (14) forms a "breadloaf" shape which can be sputter etched to seal the air gaps (17, 47). Prior to the deposition of the sputter etched silane oxide layer (14), spacers (13, 42, 43) can be formed around the interconnect lines (11, 24, 26) to increase the aspect ratio of gaps (23, 31) between the interconnect lines (11, 24, 26) which facilitates the formation of the "breadloaf" shape of the silane oxide layer (14).
摘要翻译：用于减小互连线（11,24,26）之间的电容的方法和结构利用在互连线（11,24,26）之间的气隙（17,47）。沉积在互连线（11,24,26）上，硅烷氧化物层（14）形成“面包屑”形状，其可被溅射蚀刻以密封气隙（17,47）。在沉积溅射蚀刻的硅烷氧化物层（14）之前，可以在互连线（11,24,26）周围形成间隔物（13,42,43），以增加间隙（23,31）之间的间隙（23,31）的纵横比有助于形成硅烷氧化物层（14）的“面包”形状的互连线（11,24,26）。

3. 发明授权

US07633389B2 Location enabled device with power saving control and method thereof 有权
标题翻译：具有省电控制的位置使能装置及其方法
公开(公告)号：US07633389B2
公开(公告)日：2009-12-15
申请号：US11404275
申请日：2006-04-14
申请人： Jose Ricardo B. Mantovani , Bruce A. Bernhardt
发明人： Jose Ricardo B. Mantovani , Bruce A. Bernhardt
IPC分类号： G08B1/08
CPC分类号： G08B21/0202
摘要： An energy constrained device (100) includes a motion sensor (150) operative to detect motion of the device (100); a device position determinator (130); and a controller (110) operatively coupled at the motion sensor (150) and to the device position determinator (130) and operative to receive a device location request for the energy constrained device (100), to determine whether the energy constrained device (100) has moved based on the motion sensor (150), and to determine whether to request position information from the device position determinator (130) based on device movement. A method for saving power for a device position determinator (130) in a energy constrained device (100) includes determining whether position information has been requested from the device position determinator (130); and if not so, automatically switching the device position determinator (130) to a low power consumption mode.
摘要翻译：能量约束装置（100）包括运动传感器（150），用于检测装置（100）的运动; 设备位置确定器（130）; 以及可操作地耦合在所述运动传感器（150）处并且耦合到所述设备位置确定器（130）并且可操作地接收对所述能量约束设备（100）的设备位置请求的控制器（110），以确定所述能量约束设备（100 ）已经基于运动传感器（150）移动，并且基于设备移动来确定是否从设备位置确定器（130）请求位置信息。一种用于在能量受限设备（100）中为设备位置确定器（130）节省功率的方法包括：确定是否已经从设备位置确定器（130）请求位置信息; 如果不是这样，则将设备位置确定器（130）自动切换到低功耗模式。

4. 发明授权

US5583355A Self-aligned FET having etched ohmic contacts 失效
标题翻译：具有蚀刻欧姆接触的自对准FET
公开(公告)号：US5583355A
公开(公告)日：1996-12-10
申请号：US571632
申请日：1995-12-13
申请人： Bruce A. Bernhardt , Jaeshin Cho , Gregory L. Hansell , Schyi-Yi Wu
发明人： Bruce A. Bernhardt , Jaeshin Cho , Gregory L. Hansell , Schyi-Yi Wu
IPC分类号： H01L21/285 , H01L21/338 , H01L29/45 , H01L29/812 , H01L31/0328 , H01L23/48 , H01L27/088 , H01L29/80
CPC分类号： H01L29/66878 , H01L21/28575 , H01L29/452 , H01L29/812 , Y10S148/02 , Y10S257/90
摘要： A III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to include an alloy in contact with the surface of the substrate (11). The ohmic contact (19, 20, 36, 37, 43, 44) is formed to abut the gate structure (16, 17, 18) by covering a portion of the gate structure (16, 17, 18) and the substrate (11) with the ohmic contact (19, 20, 36, 37, 43, 44), then, removing portions of the ohmic contact from the gate structure (16, 17, 18) by etching. The ohmic contact (19, 20, 36, 37, 43, 44) is formed to be substantially devoid of gold.
摘要翻译：具有蚀刻欧姆接触（19,20,36,37,43,44）的III-V半导体FET（10,30,40）。 FET（10,30,40）的栅极（16）形成为与III-V基板（11）的表面接触。产生欧姆接触（19,20,36,37,43,44）以包括与基底（11）的表面接触的合金。欧姆接触（19,20,36,37,43,44）形成为通过覆盖栅极结构（16,17,18）和基板（11）的一部分来邻接栅极结构（16,17,18））与欧姆接触（19,20,36,37,43,44），然后通过蚀刻从栅极结构（16,17,18）去除欧姆接触的部分。欧姆接触（19,20,36,37,43,44）形成为基本上不含金。

5. 发明授权

US5389564A Method of forming a GaAs FET having etched ohmic contacts 失效
标题翻译：形成具有蚀刻欧姆接触的GaAs FET的方法
公开(公告)号：US5389564A
公开(公告)日：1995-02-14
申请号：US902245
申请日：1992-06-22
申请人： Bruce A. Bernhardt , Jaeshin Cho , Gregory L. Hansell
发明人： Bruce A. Bernhardt , Jaeshin Cho , Gregory L. Hansell
IPC分类号： H01L21/285 , H01L21/338 , H01L29/45 , H01L29/812 , H01L21/265
CPC分类号： H01L29/66878 , H01L21/28575 , H01L29/452 , H01L29/812 , Y10S148/02 , Y10S257/90
摘要： The present invention provides a III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to include an alloy in contact with the surface of the substrate (11). The ohmic contact (19, 20, 36, 37, 43, 44) is formed to abut the gate structure (16, 17, 18) by covering a portion of the gate structure (16, 17, 18) and the substrate (11) with the ohmic contact (19, 20, 36, 37, 43, 44), then, removing portions of the ohmic contact from the gate structure (16, 17, 18) by etching. The ohmic contact (19, 20, 36, 37, 43, 44) is formed to be substantially devoid of gold.
摘要翻译：本发明提供具有蚀刻欧姆接触（19,20,36,37,43,44）的III-V半导体FET（10,30,40）。 FET（10,30,40）的栅极（16）形成为与III-V基板（11）的表面接触。产生欧姆接触（19,20,36,37,43,44）以包括与基底（11）的表面接触的合金。欧姆接触（19,20,36,37,43,44）形成为通过覆盖栅极结构（16,17,18）和基板（11）的一部分来邻接栅极结构（16,17,18））与欧姆接触（19,20,36,37,43,44），然后通过蚀刻从栅极结构（16,17,18）去除欧姆接触的部分。欧姆接触（19,20,36,37,43,44）形成为基本上不含金。

6. 发明授权

US5937285A Method of fabricating submicron FETs with low temperature group III-V material 失效
标题翻译：用低温III-V族材料制造亚微米FET的方法
公开(公告)号：US5937285A
公开(公告)日：1999-08-10
申请号：US863109
申请日：1997-05-23
申请人： Jonathan K. Abrokwah , Ravi Droopad , Corey D. Overgaard , Brian Bowers , Michael P. LaMacchia , Bruce A. Bernhardt
发明人： Jonathan K. Abrokwah , Ravi Droopad , Corey D. Overgaard , Brian Bowers , Michael P. LaMacchia , Bruce A. Bernhardt
IPC分类号： H01L21/20 , H01L21/335 , H01L21/8252 , H01L29/80
CPC分类号： H01L29/802 , H01L21/02395 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02631 , H01L21/8252 , H01L29/66462
摘要： A method of fabricating submicron HFETs includes forming a buffered substrate structure with a supporting substrate of GaAs, a portion of low temperature AlGaAs grown on the supporting substrate at a temperature of approximately 300.degree. C., a layer of low temperature GaAs grown on the portion AlGaAs layer at a temperature of 200.degree. C., a layer of low temperature AlGaAs grown on the GaAs layer at a temperature of 400.degree. C., and a buffer layer of undoped GaAs grown on the second AlGaAs layer. Complementary pairs of HFETs can be formed on the buffered substrate structure, since the structure supports the operation of p and n type transistors equally well.
摘要翻译：制造亚微米HFET的方法包括用GaAs的支撑衬底形成缓冲衬底结构，在约300℃的温度下在支撑衬底上生长一部分低温AlGaAs，在该部分生长的低温GaAs层 AlGaAs层，在400℃的温度下在GaAs层上生长的低温AlGaAs层和在第二AlGaAs层上生长的未掺杂的GaAs的缓冲层。可以在缓冲衬底结构上形成互补的HFET对，因为该结构同样良好地支持p型和n型晶体管的操作。

7. 发明授权

US5447874A Method for making a semiconductor device comprising a dual metal gate using a chemical mechanical polish 失效
标题翻译：使用化学机械抛光剂制造包括双金属栅极的半导体器件的方法
公开(公告)号：US5447874A
公开(公告)日：1995-09-05
申请号：US282360
申请日：1994-07-29
申请人： Gordon Grivna , Bruce A. Bernhardt , Gerald Keller
发明人： Gordon Grivna , Bruce A. Bernhardt , Gerald Keller
IPC分类号： H01L21/285 , H01L21/338 , H01L29/423 , H01L29/47
CPC分类号： H01L29/66878 , H01L21/28581 , H01L29/42316 , H01L29/475
摘要： A method of manufacturing a semiconductor device gate is provided that reduces gate length variability while maintaining self-alignment and eliminating etch damage and substrate contamination. A gate opening (18) is formed in an oxide layer (16) using a anisotropic etch. The anisotropic etch creates a reverse gate metal image that has low gate length variability. Dual metal gate (26) is then deposited. The excess gate metal is then removed and the top surface (31) of the gate (30) planarized using a chemical mechanical polish. The remaining oxide (16) is then removed, leaving a precise gate (30). The use of a nitride barrier (12) and of an etchstop layer (14) of aluminum nitride under the oxide layer (16) is also shown.
摘要翻译：提供一种制造半导体器件栅极的方法，其在保持自对准并消除蚀刻损伤和衬底污染的同时减小栅极长度变化。使用各向异性蚀刻在氧化物层（16）中形成栅极开口（18）。各向异性蚀刻产生具有低栅极长度可变性的反向栅极金属图像。然后沉积双金属栅极（26）。然后去除多余的栅极金属，并且使用化学机械抛光将栅极（30）的顶表面（31）平坦化。然后去除剩余的氧化物（16），留下精确的浇口（30）。还示出了在氧化物层（16）下使用氮化物阻挡层（12）和氮化铝的蚀刻阻挡层（14）。

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