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    • 1. 发明授权
    • Pad and cable geometries for spring clip mounting and electrically connecting flat flexible multiconductor printed circuit cables to switching chips on spaced-parallel planar modules
    • 用于弹簧夹安装的焊盘和电缆几何形状,并将扁平柔性多导体印刷电路电缆电连接到间隔平行平面模块上的切换芯片
    • US06301247B1
    • 2001-10-09
    • US09426501
    • 1999-10-26
    • Brian Ralph LarsonCharles Kryzak
    • Brian Ralph LarsonCharles Kryzak
    • H04L1250
    • H04L49/45H04L49/1515H04L49/309H04L2012/5627
    • Dense physical and electrical connection of (i) flat flexible multiconductor cables of the printed circuit or ribbon types, to (ii) to spaced-parallel planar modules, particularly to switching modules containing switching chips, is realized by (1) a particular connection geometry in combination with (2) a spring clip connector. Flat flexible multiconductor cables routed through free space either in (i) “X” and, optionally also, “Z” planes, or else in (ii) “Y” planes exclusively, have their conductors' ends stripped and bent 90° so as to lie upon conductive pads, arrayed along lines angled 45° to both the “X” and “Y” planes, located on the substrates of switching modules that are within “Z” planes. A substantially square, substantially planar, spring clip mounts and re-mounts to the substrate by, preferably, two tabs fitting in a corresponding two holes in the substrate, so as to hold exposed conductor ends of each cable bent 90° compressively against a portion of the arrayed conductive pads, making electrical connections.
    • (i)印刷电路或色带类型的扁平柔性多导体电缆的密集物理和电气连接,通过(1)特定的连接几何形状实现(ii)到间隔平行的平面模块,特别是包含开关芯片的开关模块 与(2)弹簧夹连接器组合。 扁平柔性多导体电缆通过(i)“X”和(可选地)“Z”平面或另外在(ii)“Y”平面中的自由空间布线,其导线端部被剥离并弯曲90°,以便 位于导电焊盘上,沿着与“Z”平面内的开关模块的基板上的“X”和“Y”平面成45°角的线排列。 基本上为方形的,基本上平面的弹簧夹通过优选地安装在衬底中并重新安装到衬底,优选地,两个接头嵌合在衬底中的相应的两个孔中,以便将每个电缆弯曲90°的每个电缆的暴露的导体端部压缩抵抗部分 的阵列导电焊盘,进行电气连接。
    • 2. 发明授权
    • Three-dimensional interconnection geometries for multi-stage switching networks using flexible ribbon cable connection between multiple planes
    • 用于多层交换网络的三维互连几何,使用多个平面之间的柔性带状电缆连接
    • US06504841B1
    • 2003-01-07
    • US09426466
    • 1999-10-26
    • Brian Ralph LarsonCharles Kryzak
    • Brian Ralph LarsonCharles Kryzak
    • H04L1250
    • H04L49/45H04L49/1515H04L49/309H04L2012/5627
    • Scalable Computer Interconnect (CSI) compliant multi-stage switching networks compactly electrically communicatively interconnect a large number N of electrically communicating devices, typically computers or memories, in three-dimensional space. The logic networks, including a preferred “layered network” of U.S. Pat. No. 4,833,468, are (i) rotated, (ii) folded and (iii) squared per companion U.S. Pat. No. 6,301,247 so as to assume optimal topology. The topologically-optimized switching network logic is physically realized as (i) planar panels each mounting multi-chip modules, or tiles, each having logic switchpoints each realized by switch dice, plus vias through the tiles, plus pads upon both sides of the tiles, plus connective wiring layers upon the tile, connected by (ii) multi-conductor flexible flat printed circuit cables located between the adjacent panels. System peak performance is 24 teraflops/second.
    • 可扩展计算机互连(CSI)兼容的多级交换网络在三维空间中紧密地电通信地将大量N个电通信设备(通常为计算机或存储器)互连。 逻辑网络,包括美国专利的优选“分层网络” (i)旋转,(ii)折叠,(iii)每个伴侣美国专利。 6,301,247,以便采取最佳的拓扑结构。 拓扑优化的交换网络逻辑在物理上实现为:(i)平面板,每个安装多个芯片模块或瓦片,每个具有逻辑切换点,每个逻辑切换点各自由开关骰子实现,加上通过瓦片的通孔,以及瓦片两侧的焊盘 ,以及瓦片上的连接布线层,由(ii)位于相邻面板之间的多导体柔性平面印刷电路电缆连接。 系统峰值性能为24 teraflops /秒。
    • 7. 发明授权
    • Dance/multitude concurrent computation
    • 舞蹈/多重并发计算
    • US5867649A
    • 1999-02-02
    • US589933
    • 1996-01-23
    • Brian Ralph Larson
    • Brian Ralph Larson
    • G06F9/44G06F15/16
    • G06F8/314
    • This invention computes by constructing a lattice of states. Every lattice of states corresponding to correct execution satisfies the temporal logic formula comprising a Definitive Axiomatic Notation for Concurrent Execution (DANCE) program. This invention integrates into a state-lattice computational model: a polymorphic, strong type system; visibility-limiting domains; first-order assertions; and logic for proving a program correctness. This invention includes special hardware means for elimination of cache coherency among other things, necessary to construct state-lattices concurrently. The model of computation for the DANCE language consisting of four, interrelated, logical systems describing state-lattices, types, domains, and assertions. A fifth logical system interrelates the other four systems allowing proofs of program correctness. The method of the present invention teaches programs as temporal formulas satisfied by lattices of states corresponding to correct execution. State-lattices that are short and bushy allow application of many processors simultaneously thus reducing execution time.
    • 本发明通过构造状态的格子来计算。 对应于正确执行的每个格状态都满足包括用于并行执行(DANCE)程序的确定公理符号的时间逻辑公式。 本发明集成为状态格计算模型:多态,强类型系统; 可见性限制域; 一级断言; 以及证明程序正确性的逻辑。 本发明包括用于消除高速缓存一致性的特殊硬件装置,其是同时构建状态网格所必需的。 DANCE语言的计算模型由描述状态格式,类型,域和断言的四个相互关联的逻辑系统组成。 第五个逻辑系统将其他四个系统相互关联,从而允许程序正确性的证明。 本发明的方法教导程序作为与正确执行相对应的状态格子满足的时间公式。 短而浓密的状态允许同时应用许多处理器,从而减少执行时间。