会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 7. 发明授权
    • Reduced lock time for a phase locked loop
    • 减少锁相环的锁定时间
    • US06380810B1
    • 2002-04-30
    • US09645212
    • 2000-08-24
    • Brian P. Sutton
    • Brian P. Sutton
    • H03L7093
    • H03L7/189H03L2207/06
    • A reduced lock time phase locked loop has a speed up circuit with an operational amplifier to amplify a differential voltage across a filter resistor of an RC noise filter, the RC noise filter coupling a coarse tune voltage to a VCO. The amplifed differential voltage is applied to the bases of a pair of opposite polarity transistors, the emitters of the transistors being coupled to a filter capacitor in the RC noise filter for rapid charging/discharging. Alternatively the amplified differential voltage is applied to a pair of parallel, opposite polarity diodes coupled to the filter capacitor for rapid charging/discharging.
    • 缩短的锁定时间锁相环具有运算放大器的加速电路,以放大RC噪声滤波器的滤波电阻上的差分电压,RC噪声滤波器将粗调电压耦合到VCO。 放大的差分电压被施加到一对相反极性晶体管的基极,晶体管的发射极耦合到RC噪声滤波器中的滤波电容器,用于快速充电/放电。 或者,放大的差分电压被施加到耦合到滤波电容器的一对并联的相反极性二极管,用于快速充电/放电。