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1. 发明申请

US20060001105A1 Semiconductor device having optimized shallow junction geometries and method for fabrication thereof 审中-公开
公开(公告)号：US20060001105A1
公开(公告)日：2006-01-05
申请号：US11179210
申请日：2005-07-12
申请人： Brian Hornung , Xin Zhang , Lance Robertson , Srinivasan Chakravarthi , P. Chidambaram
发明人： Brian Hornung , Xin Zhang , Lance Robertson , Srinivasan Chakravarthi , P. Chidambaram
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L21/823864
摘要： The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134). Other embodiments of the present invention include a transistor device (200) and method of manufacturing an integrated circuit (300).

2. 发明申请

US20050245021A1 Semiconductor device having optimized shallow junction geometries and method for fabrication thereof 有权
标题翻译：具有优化的浅结几何形状的半导体器件及其制造方法
公开(公告)号：US20050245021A1
公开(公告)日：2005-11-03
申请号：US10835121
申请日：2004-04-29
申请人： Brian Hornung , Xin Zhang , Lance Robertson , Srinivasan Chakravarthi , P.R. Chidambaram
发明人： Brian Hornung , Xin Zhang , Lance Robertson , Srinivasan Chakravarthi , P.R. Chidambaram
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823864
摘要： The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134). Other embodiments of the present invention include a transistor device (200) and method of manufacturing an integrated circuit (300).
摘要翻译：本发明在一个实施例中提供一种制造半导体器件（100）的方法。该方法包括在栅极结构（114）和衬底（102）上生长氧化物层（120）并将掺杂剂（124）注入到衬底（102）和氧化物层（120）中。注入使得掺杂剂（124）的一部分保留在氧化物层（120）中以形成注入的氧化物层（126）。该方法还包括在注入的氧化物层（126）上沉积保护性氧化物层（132）并且形成耐腐蚀的偏置间隔物（134）。在栅极结构（114）的侧壁和保护氧化物层（132）上形成耐蚀刻偏置间隔物（134）。耐腐蚀的偏置间隔件具有邻近侧壁的内周边（135）和相对的外周边（136）。该方法还包括去除位于耐蚀刻偏移间隔物（134）的外周（136）外的保护氧化物层（132）的部分。本发明的其他实施例包括晶体管器件（200）和制造集成电路（300）的方法。

3. 发明申请

US20070066024A1 Phosphorus Activated NMOS Using SiC Process 审中-公开
公开(公告)号：US20070066024A1
公开(公告)日：2007-03-22
申请号：US11558179
申请日：2006-11-09
申请人： Srinivasan Chakravarthi , P. Chidambaram
发明人： Srinivasan Chakravarthi , P. Chidambaram
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66651
摘要： A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure (114). Source and drain regions (140, 142) are then formed (26) within the semiconductor substrate (102) on opposing sides of the channel (122) with a phosphorus dopant.

4. 发明授权

US06797593B2 Methods and apparatus for improved mosfet drain extension activation 有权
标题翻译：改善mosfet漏极扩展激活的方法和装置
公开(公告)号：US06797593B2
公开(公告)日：2004-09-28
申请号：US10243610
申请日：2002-09-13
申请人： Srinivasan Chakravarthi , Amitabh Jain , Xin Zhang
发明人： Srinivasan Chakravarthi , Amitabh Jain , Xin Zhang
IPC分类号： H01L21425
CPC分类号： H01L29/6653 , H01L21/26513 , H01L21/324 , H01L29/665 , H01L29/6659
摘要： Methods are described for fabricating MOS type transistors, in which multiple drain extension implants are performed using different dopant species of the same type. The implanted drain extension dopants are activated using separate anneal processes to provide active dopants of both species throughout the drain extension regions adjacent the transistor channel.
摘要翻译：描述了用于制造MOS型晶体管的方法，其中使用相同类型的不同掺杂剂种类来执行多个漏极延伸注入。注入的漏极延伸掺杂剂使用单独的退火工艺来激活，以在与晶体管沟道相邻的漏极延伸区域提供两种物质的有源掺杂剂。

5. 发明申请

US20060017079A1 N-type transistor with antimony-doped ultra shallow source and drain 审中-公开
标题翻译：具有锑掺杂超浅源极和漏极的N型晶体管
公开(公告)号：US20060017079A1
公开(公告)日：2006-01-26
申请号：US10896421
申请日：2004-07-21
申请人： Srinivasan Chakravarthi , Amitabh Jain , Xin Zhang
发明人： Srinivasan Chakravarthi , Amitabh Jain , Xin Zhang
IPC分类号： H01L29/76 , H01L21/425 , H01L31/117 , H01L21/44
CPC分类号： H01L21/26513 , H01L21/02667 , H01L21/2022 , H01L21/26506 , H01L29/66575 , H01L29/78
摘要： We disclose a process for forming ultra shallow n+p junctions. The junction is formed by, for example, implanting 3E14 ions/cm2 of antimony ions at 5 keV into silicon. The silicon is pre-amorphized by a previous ion-implantation. The pre-amorphizing implant species may be germanium or arsenic. Germanium may be implanted at 15 keV and Arsenic may be implanted at 2 keV. Both the pre-amorphizing implant and the antimony implant are preferably through bare silicon surface—not covered with any foreign material with the exception of possibly a layer of native oxide. The junction is annealed at about 950° C. following the implants to re-crystallize the implanted region and to activate the implanted ions. The ultra shallow junction is superior because it has a abrupt junction, high sheet resistance and can be formed with low thermal budget.
摘要翻译：我们公开了形成超浅层p + p结的方法。该结通过例如以5keV将3E14离子/ cm 2的锑离子注入到硅中而形成。硅通过先前的离子注入而被非晶化。前非晶化植入物种可以是锗或砷。锗可以以15keV注入，砷可以以2keV注入。预非晶化植入物和锑植入物优选通过裸露的硅表面 - 未被任何异物覆盖，除了可能的一层天然氧化物之外。接合点在大约950℃下退火，在植入物重新结晶植入区域并激活注入的离子之后。超浅结是优越的，因为其具有突然的接合，高的薄层电阻，并且可以以低的热预算形成。

6. 发明授权

US07033879B2 Semiconductor device having optimized shallow junction geometries and method for fabrication thereof 有权
标题翻译：具有优化的浅结几何形状的半导体器件及其制造方法
公开(公告)号：US07033879B2
公开(公告)日：2006-04-25
申请号：US10835121
申请日：2004-04-29
申请人： Brian E. Hornung , Xin Zhang , Lance S. Robertson , Srinivasan Chakravarthi , Beriannan Chidambaram
发明人： Brian E. Hornung , Xin Zhang , Lance S. Robertson , Srinivasan Chakravarthi , Beriannan Chidambaram
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823864
摘要： The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134). Other embodiments of the present invention include a transistor device (200) and method of manufacturing an integrated circuit (300).
摘要翻译：本发明在一个实施例中提供一种制造半导体器件（100）的方法。该方法包括在栅极结构（114）和衬底（102）上生长氧化物层（120）并将掺杂剂（124）注入到衬底（102）和氧化物层（120）中。注入使得掺杂剂（124）的一部分保留在氧化物层（120）中以形成注入的氧化物层（126）。该方法还包括在注入的氧化物层（126）上沉积保护性氧化物层（132）并且形成耐腐蚀的偏置间隔物（134）。在栅极结构（114）的侧壁和保护氧化物层（132）上形成耐蚀刻偏置间隔物（134）。耐腐蚀的偏置间隔件具有邻近侧壁的内周边（135）和相对的外周边（136）。该方法还包括去除位于耐蚀刻偏移间隔物（134）的外周（136）外的保护氧化物层（132）的部分。本发明的其他实施例包括晶体管器件（200）和制造集成电路（300）的方法。

7. 发明授权

US09048180B2 Low stress sacrificial cap layer 有权
标题翻译：低应力牺牲帽层
公开(公告)号：US09048180B2
公开(公告)日：2015-06-02
申请号：US11383721
申请日：2006-05-16
申请人： Jiong-Ping Lu , Periannan Chidambaram , Srinivasan Chakravarthi
发明人： Jiong-Ping Lu , Periannan Chidambaram , Srinivasan Chakravarthi
IPC分类号： H01L21/02 , H01L21/265 , H01L21/318 , H01L21/324 , H01L29/66
CPC分类号： H01L21/26513 , H01L21/3185 , H01L21/324 , H01L29/6656 , H01L29/6659
摘要： A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300, 500 for fabricating a transistor 20, 400 having a low stress sacrificial cap layer 120, 410.
摘要翻译：具有氧化硅衬垫膜130，低应力硅膜140和氮化硅膜的低应力牺牲帽层120或者，具有氧化硅衬垫膜130和梯度氮化硅膜420的低应力牺牲帽层410 而且，用于制造具有低应力牺牲帽层120,410的晶体管20,400的方法300,500。

8. 发明申请

US20090170256A1 ANNEALING METHOD FOR SIGE PROCESS 审中-公开
标题翻译：用于信号处理的退火方法
公开(公告)号：US20090170256A1
公开(公告)日：2009-07-02
申请号：US12206456
申请日：2008-09-08
申请人： Srinivasan Chakravarthi , Haowen Bu , Periannan Chidambaram
发明人： Srinivasan Chakravarthi , Haowen Bu , Periannan Chidambaram
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/268 , H01L21/2686 , H01L21/324 , H01L21/823807 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of forming a transistor comprising forming a gate structure over an n-type semiconductor body and forming recesses substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown in the recesses and a silicon cap layer is formed over the silicon germanium. Further introduction of impurities into the silicon germanium to increase the melting point thereof and implanting p-type source/drain regions in the semiconductor body is included in the method. The method concludes with performing a high temperature thermal treatment.
摘要翻译：一种形成晶体管的方法，包括在n型半导体本体上形成栅极结构，并形成与半导体本体中的栅极结构基本对准的凹槽。然后在凹槽中外延生长硅锗，并在硅锗上形成硅帽层。在该方法中包括将杂质进一步引入硅锗以增加其熔点并在半导体本体中注入p型源/漏区。该方法的结论是进行高温热处理。

9. 发明申请

US20090045472A1 Methodology for Reducing Post Burn-In Vmin Drift 审中-公开
标题翻译：降低后燃烧Vmin漂移的方法
公开(公告)号：US20090045472A1
公开(公告)日：2009-02-19
申请号：US11837709
申请日：2007-08-13
申请人： Srinivasan Chakravarthi , Narendra Singh Mehta , Rajesh Khamankar , Ajith Varghese , Malcolm J. Bevan , Tad Grider
发明人： Srinivasan Chakravarthi , Narendra Singh Mehta , Rajesh Khamankar , Ajith Varghese , Malcolm J. Bevan , Tad Grider
IPC分类号： H01L29/94 , H01L21/8234
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes source/drain regions formed in a substrate and having a concentration of nitrogen of at least about 5E18 cm−3. A gate dielectric is located over the substrate and between the source/drain regions. Gate sidewall spacers are located over said source/drain regions. A nitrogen-doped electrode including polysilicon is located over the gate dielectric. The electrode has a concentration of nitrogen therein greater than the concentration of nitrogen in the source/drain regions.
摘要翻译：半导体器件包括形成在衬底中并具有至少约5E18cm-3的氮浓度的源极/漏极区域。栅极电介质位于衬底上并且在源/漏区之间。栅极侧壁间隔物位于所述源极/漏极区域之上。包括多晶硅的氮掺杂电极位于栅极电介质上方。电极的氮浓度大于源极/漏极区域中的氮浓度。

10. 发明申请

US20080277699A1 Recess Etch for Epitaxial SiGe 有权
标题翻译：外延SiGe的凹陷蚀刻
公开(公告)号：US20080277699A1
公开(公告)日：2008-11-13
申请号：US11747708
申请日：2007-05-11
申请人： Srinivasan Chakravarthi , Periannan Chidambaram , Johan Weijtmans
发明人： Srinivasan Chakravarthi , Periannan Chidambaram , Johan Weijtmans
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/3065 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer.
摘要翻译：一种PMOS晶体管及其制造方法。该方法可以包括提供具有PMOS晶体管栅极叠层，源极/漏极延伸区域和有源区域的半导体晶片。该方法还可以包括形成外壁侧壁，执行非原位凹槽蚀刻以及进行原位凹槽蚀刻。原位凹槽蚀刻和原位凹陷蚀刻形成凹陷的有源区。 PMOS晶体管通过使用非原位和原位蚀刻的方法形成，并且具有在半导体晶片的表面处具有最大宽度的外延SiGe区域。

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