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1. 发明申请

US20120089792A1 EFFICIENT IMPLEMENTATION OF ARRAYS OF STRUCTURES ON SIMT AND SIMD ARCHITECTURES 有权
标题翻译：对SIMT和SIMD建筑结构的有效实施
公开(公告)号：US20120089792A1
公开(公告)日：2012-04-12
申请号：US13247855
申请日：2011-09-28
申请人： Brian FAHS , John R. Nickolls , Kathleen Elliott Nickolls , Henry Packard Moreton , Brett W. Coon
发明人： Brian FAHS , John R. Nickolls , Kathleen Elliott Nickolls , Henry Packard Moreton , Brett W. Coon
IPC分类号： G06F12/00
CPC分类号： G06F9/3885 , G06F9/30036 , G06F9/3009 , G06F9/30123 , G06F9/345 , G06F9/3824 , G06F9/3851 , G06F9/3887 , G06F12/0207 , G06T1/20
摘要： One embodiment of the present invention sets forth a technique providing an optimized way to allocate and access memory across a plurality of thread/data lanes. Specifically, the device driver receives an instruction targeted to a memory set up as an array of structures of arrays. The device driver computes an address within the memory using information about the number of thread/data lanes and parameters from the instruction itself. The result is a memory allocation and access approach where the device driver properly computes the target address in the memory. Advantageously, processing efficiency is improved where memory in a parallel processing subsystem is internally stored and accessed as an array of structures of arrays, proportional to the SIMT/SIMD group width (the number of threads or lanes per execution group).
摘要翻译：本发明的一个实施例提出了一种技术，其提供了一种在多个线程/数据通道上分配和访问存储器的优化方式。具体来说，设备驱动程序接收到作为阵列结构的阵列设置的存储器的指令。设备驱动程序使用关于指令本身的线程/数据通道数和参数的信息来计算存储器中的地址。结果是存储器分配和访问方法，其中设备驱动器正确地计算存储器中的目标地址。有利的是，处理效率得到改善，其中并行处理子系统中的存储器被内部存储和访问为与SIMT / SIMD组宽度（每个执行组的线程或通道数）成比例的阵列结构的阵列。

2. 发明申请

US20110078417A1 COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS 有权
标题翻译：合作螺线减排和扫描作业
公开(公告)号：US20110078417A1
公开(公告)日：2011-03-31
申请号：US12890227
申请日：2010-09-24
申请人： Brian FAHS , Ming Y. Siu , Brett W. Coon , John R. Nickolls , Lars Nyland
发明人： Brian FAHS , Ming Y. Siu , Brett W. Coon , John R. Nickolls , Lars Nyland
IPC分类号： G06F9/38
CPC分类号： G06F9/522 , G06F8/458 , G06F9/3004 , G06F9/30087 , G06F9/30145 , G06F9/3851
摘要： One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread.
摘要翻译：本发明的一个实施例提出了一种用于跨独立执行的多个线程执行聚合操作的技术。聚合被指定为屏障同步或屏障到达指令的一部分，其中除了执行屏障同步或到达之外，指令聚合（使用缩减或扫描操作）由每个线程提供的值。当线程执行屏障聚合指令时，线程有助于扫描或缩小结果，并等待执行任何更多指令，直到所有线程都执行了阻挡聚合指令为止。在所有线程执行了屏障聚合指令之后，向每个线程传送减少结果，并且当线程执行屏障聚合指令时，将扫描结果传送给每个线程。

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