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1. 发明授权

US08793462B2 Implementing storage adapter performance optimization with enhanced resource pool allocation 有权
标题翻译：通过增强资源池分配来实现存储适配器性能优化
公开(公告)号：US08793462B2
公开(公告)日：2014-07-29
申请号：US13114427
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F3/0617 , G06F3/0631 , G06F3/0689
摘要： A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance.
摘要翻译：一种用于实现具有增强的资源池分配的存储适配器性能优化的方法和控制器，以及提供主题控制器电路所在的设计结构。控制器包括多个硬件引擎; 处理器和多个资源池。多个工作队列与资源池相关联。处理器初始化类型列表，以及每种分配类型的相关联的页面数量。硬件引擎维护分配类型的计数，指定每个分配和解除分配的类型，并从资源池执行死锁避免的分配。

2. 发明申请

US20120303859A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH PARITY UPDATE FOOTPRINT MIRRORING 有权
标题翻译：实现存储适配器性能优化与更新FOOTPRINT MIRRORING
公开(公告)号：US20120303859A1
公开(公告)日：2012-11-29
申请号：US13114268
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/00
CPC分类号： G06F11/1076 , G06F11/1666 , G06F11/2089 , G06F11/2097 , G06F2211/1009 , G06F2211/1057 , G06F2211/1059
摘要： A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其中，具有奇偶校验更新占用面积的双重适配器之间的镜像，最小化固件操作，以及提供了主题控制器电路所在的设计结构。第一控制器和第二控制器中的每一个包括多个硬件引擎，配置为存储奇偶校验更新占位（PUFP）数据的控制存储器; 数据存储和非易失性随机存取存储器（NVRAM）。一个控制器以第一启动器模式操作，用于将PUFP数据传送到以目标模式操作的另一个控制器。各启动器硬件引擎从启动器控制存储器传输PUFP数据，选择性地更新PUFP数据，并将PUFP数据写入发起者数据存储器和发起者NVRAM，同时将PUFP数据传输到另一个控制器。各个目标硬件引擎将PUFP数据写入目标数据存储和目标NVRAM，从而消除了固件操作。

3. 发明授权

US08495258B2 Implementing storage adapter performance optimization with hardware accelerators offloading firmware for buffer allocation and automatically DMA 失效
标题翻译：实现存储适配器性能优化与硬件加速器卸载固件的缓冲区分配和自动DMA
公开(公告)号：US08495258B2
公开(公告)日：2013-07-23
申请号：US13114124
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其具有消除固件操作的自动链接硬件操作以及提供主题控制器电路所在的设计结构。控制器包括多个硬件引擎和被配置为存储多个控制块的控制存储器。每个控制块被设计成控制多个硬件引擎之一的硬件操作。多个控制块被选择性地布置在相应的预定链中以定义硬件操作的顺序。自动硬件结构被配置为构建控制用于预定义硬件功能的硬件操作的相应预定义链。预定义的硬件功能包括从主机系统到控制器的写入操作的缓冲区分配和自动DMA数据，从而消除了固件操作。

4. 发明申请

US20120303883A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CACHE DATA/DIRECTORY MIRRORING 有权
标题翻译：使用缓存数据/目录映射实现存储适配器性能优化
公开(公告)号：US20120303883A1
公开(公告)日：2012-11-29
申请号：US13114185
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/00 , G06F11/108 , G06F11/2071 , G06F12/08 , G06F12/0868 , G06F2211/1009 , G06F2211/1059 , G06F2212/1016 , G06F2212/225 , G06F2212/286
摘要： A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其中缓存数据和双重适配器之间的缓存目录镜像最小化固件操作，以及提供主题控制器电路所在的设计结构。第一控制器或第二控制器中的一个以第一启动器模式操作，包括固件，用于建立向每个页索引建立数据帧的启动器写入操作和用于每个页索引的相应高速缓存行（CL）到另一控制器第二目标模式。各发起者硬件引擎传送数据，从启动器控制存储器读取CL，并将更新后的CL写入发起者数据存储器，同时向其他控制器发送数据和更新的CL。各个目标硬件引擎将数据和更新的CL写入目标数据存储，消除了在第二目标模式下操作的控制器的固件操作。

5. 发明申请

US20120297272A1 IMPLEMENTING ENHANCED IO DATA CONVERSION WITH PROTECTION INFORMATION MODEL INCLUDING PARITY FORMAT OF DATA INTEGRITY FIELDS 有权
标题翻译：实施具有保护信息模型的增强IO数据转换，包括数据完整性字段的特殊格式
公开(公告)号：US20120297272A1
公开(公告)日：2012-11-22
申请号：US13108097
申请日：2011-05-16
申请人： Brian E. Bakke , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Rick A. Weckwerth
发明人： Brian E. Bakke , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Rick A. Weckwerth
IPC分类号： G06F11/20
CPC分类号： G06F11/1076
摘要： A method and controller for implementing enhanced input/output (IO) data conversion with an enhanced protection information model including an enhanced parity format of the data integrity fields (DIF), and a design structure on which the subject controller circuit resides are provided. The controller implements a protection information model including a unique parity data integrity fields (DIF) format. The unique parity DIF format enables corruption detection for RAID parity blocks. The unique parity DIF format includes a predefined size for a protection information model logical block guard cyclic redundancy check (CRC) field and a logical block Reference Tag (RT) field. A plurality of storage devices in a RAID configuration are coupled to the controller, and configured to store data and RAID parity redundancy data, and wherein a strength of RAID parity redundancy data is not reduced when a loss of a single storage device in the plurality of storage devices occurs.
摘要翻译：一种用于通过增强的保护信息模型实现增强的输入/输出（IO）数据转换的方法和控制器，该增强的保护信息模型包括数据完整性字段（DIF）的增强的奇偶校验格式，以及提供了对象控制器电路所在的设计结构。控制器实现包括唯一奇偶校验数据完整性字段（DIF）格式的保护信息模型。唯一的奇偶校验DIF格式可以对RAID奇偶校验块进行故障检测。唯一奇偶校验DIF格式包括用于保护信息模型逻辑块保护循环冗余校验（CRC）字段和逻辑块参考标签（RT）字段的预定义大小。 RAID配置中的多个存储设备被耦合到控制器，并且被配置为存储数据和RAID奇偶校验冗余数据，并且其中当多个存储设备中的单个存储设备的丢失时，RAID奇偶校验冗余数据的强度不会降低存储设备发生。

6. 发明授权

US08886881B2 Implementing storage adapter performance optimization with parity update footprint mirroring 有权
标题翻译：实现具有奇偶校验更新占用空间镜像的存储适配器性能优化
公开(公告)号：US08886881B2
公开(公告)日：2014-11-11
申请号：US13114268
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F11/20 , G06F11/10 , G06F11/16
CPC分类号： G06F11/1076 , G06F11/1666 , G06F11/2089 , G06F11/2097 , G06F2211/1009 , G06F2211/1057 , G06F2211/1059
摘要： A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其具有奇偶校验更新占用面积的双重适配器最小化固件操作之间的镜像，以及提供主题控制器电路所在的设计结构。第一控制器和第二控制器中的每一个包括多个硬件引擎，配置为存储奇偶校验更新占位（PUFP）数据的控制存储器; 数据存储和非易失性随机存取存储器（NVRAM）。一个控制器以第一启动器模式操作，用于将PUFP数据传送到以目标模式操作的另一个控制器。各启动器硬件引擎从启动器控制存储器传输PUFP数据，选择性地更新PUFP数据，并将PUFP数据写入发起者数据存储器和发起者NVRAM，同时将PUFP数据传输到另一个控制器。各个目标硬件引擎将PUFP数据写入目标数据存储和目标NVRAM，从而消除了固件操作。

7. 发明授权

US08516164B2 Implementing storage adapter performance optimization with enhanced hardware and software interface 失效
标题翻译：通过增强的硬件和软件接口实现存储适配器性能优化
公开(公告)号：US08516164B2
公开(公告)日：2013-08-20
申请号：US13114390
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F13/28
CPC分类号： G06F3/0689 , G06F3/0611 , G06F3/0658 , G06F3/0659 , G06F11/108 , G06F2211/1009
摘要： A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor.
摘要翻译：一种用于实现具有链接硬件操作的存储适配器性能优化的方法和控制器以及最小化硬件和固件交互的增强的硬件（HW）和固件（FW）接口，以及提供主题控制器电路所在的设计结构。控制器包括多个硬件引擎; 和处理器。数据存储器被配置为存储多个控制块。全局工作队列包括选择性地布置在预定义链中以定义硬件操作序列的多个控制块。全局工作队列包括耦合到处理器和硬件引擎的队列输入以及耦合到硬件引擎的输出。控制块被布置在各自的引擎工作队列中，其被设计成控制各个硬件引擎的硬件操作，并且各个控制块被布置在事件队列中以向处理器提供完成结果。

8. 发明授权

US08495469B2 Implementing enhanced IO data conversion with protection information model including parity format of data integrity fields 有权
标题翻译：使用包括数据完整性字段奇偶校验格式的保护信息模型来实现增强的IO数据转换
公开(公告)号：US08495469B2
公开(公告)日：2013-07-23
申请号：US13108097
申请日：2011-05-16
申请人： Brian E. Bakke , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Rick A. Weckwerth
发明人： Brian E. Bakke , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Rick A. Weckwerth
IPC分类号： G06F12/00 , G06F11/00 , G11B5/00
CPC分类号： G06F11/1076
摘要： A method and controller for implementing enhanced input/output (IO) data conversion with an enhanced protection information model including an enhanced parity format of the data integrity fields (DIF), and a design structure on which the subject controller circuit resides are provided. The controller implements a protection information model including a unique parity data integrity fields (DIF) format. The unique parity DIF format enables corruption detection for RAID parity blocks. The unique parity DIF format includes a predefined size for a protection information model logical block guard cyclic redundancy check (CRC) field and a logical block Reference Tag (RT) field. A plurality of storage devices in a RAID configuration are coupled to the controller, and configured to store data and RAID parity redundancy data, and wherein a strength of RAID parity redundancy data is not reduced when a loss of a single storage device in the plurality of storage devices occurs.
摘要翻译：一种用于通过增强的保护信息模型实现增强的输入/输出（IO）数据转换的方法和控制器，该增强的保护信息模型包括数据完整性字段（DIF）的增强的奇偶校验格式，以及提供了对象控制器电路所在的设计结构。控制器实现包括唯一奇偶校验数据完整性字段（DIF）格式的保护信息模型。唯一的奇偶校验DIF格式可以对RAID奇偶校验块进行故障检测。唯一奇偶校验DIF格式包括用于保护信息模型逻辑块保护循环冗余校验（CRC）字段和逻辑块参考标签（RT）字段的预定义大小。 RAID配置中的多个存储设备被耦合到控制器，并且被配置为存储数据和RAID奇偶校验冗余数据，并且其中当多个存储设备中的单个存储设备的丢失时，RAID奇偶校验冗余数据的强度不会降低存储设备发生。

9. 发明申请

US20120304198A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS MINIMIZING HARDWARE/FIRMWARE INTERACTIONS 有权
标题翻译：实施存储适配器性能优化与链接硬件操作最小化硬件/固件交互
公开(公告)号：US20120304198A1
公开(公告)日：2012-11-29
申请号：US13114107
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F9/44
CPC分类号： G06F3/0611 , G06F3/0656 , G06F3/0689
摘要： A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其具有最小化硬件和固件交互的链接硬件操作，以及提供主题控制器电路驻留的设计结构。控制器包括多个硬件引擎; 和一个或多个处理器。事件队列被耦合到至少一个处理器通知多个预定义事件的处理器。控制块被设计成控制多个硬件引擎中的一个的操作，包括写入事件队列条目的硬件引擎。多个控制块被选择性地布置在预定义的链中以最小化硬件引擎将事件队列条目写入处理器。

10. 发明申请

US20120303855A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE ACCELERATORS OFFLOADING FIRMWARE FOR BUFFER ALLOCATION AND AUTOMATICALLY DMA 失效
标题翻译：实施存储适配器性能优化与硬件加速器卸载固件，用于缓冲区分配和自动DMA
公开(公告)号：US20120303855A1
公开(公告)日：2012-11-29
申请号：US13114124
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其具有消除固件操作的自动链接硬件操作以及提供主题控制器电路所在的设计结构。控制器包括多个硬件引擎和被配置为存储多个控制块的控制存储器。每个控制块被设计成控制多个硬件引擎之一的硬件操作。多个控制块被选择性地布置在相应的预定链中以定义硬件操作的顺序。自动硬件结构被配置为构建控制用于预定义硬件功能的硬件操作的相应预定义链。预定义的硬件功能包括从主机系统到控制器的写入操作的缓冲区分配和自动DMA数据，从而消除了固件操作。

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