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1. 发明授权

US09455011B2 Methods and systems to read a magnetic tunnel junction (MTJ) based memory cell based on a pulsed read current 有权
标题翻译：基于脉冲读取电流读取基于磁隧道结（MTJ）的存储单元的方法和系统
公开(公告)号：US09455011B2
公开(公告)日：2016-09-27
申请号：US14350997
申请日：2012-03-25
申请人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
发明人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
IPC分类号： G11C11/00 , G11C11/16 , G11C5/12 , G11C13/00
CPC分类号： G11C11/165 , G11C5/12 , G11C11/1673 , G11C11/1693 , G11C2013/0052 , G11C2013/0071
摘要： Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.
摘要翻译：基于脉冲读取电流读取存储在基于磁隧道结（MTJ）的存储单元中的逻辑值的方法和系统，脉冲之间的时间允许MTJ朝向脉冲之间的磁化取向松弛，这可以减少构建 - MTJ内的动量，并且其可以减少和/或消除磁化取向的无意重新对准。对称和/或非对称脉冲的序列可以被施加到字线（WL），以使预充电位线（BL）电容放电通过MTJ的脉冲读取电流，从而产生相应的电压变化序列在BL上。可以在读取电流脉冲的序列上积分BL电压变化，并且可以基于积分的电压变化来确定存储的逻辑值。预充电的BL电容也可以用作电压积分器。

2. 发明授权

US08980650B2 Perpendicular MTJ stacks with magnetic anisotropy enhancing layer and crystallization barrier layer 有权
标题翻译：具有磁各向异性增强层和结晶阻挡层的垂直MTJ叠层
公开(公告)号：US08980650B2
公开(公告)日：2015-03-17
申请号：US14454682
申请日：2014-08-07
申请人： Kaan Oguz , Mark L. Doczy , Brian Doyle , Uday Shah , David L. Kencke , Roksana Golizadeh Mojarad , Robert S. Chau
发明人： Kaan Oguz , Mark L. Doczy , Brian Doyle , Uday Shah , David L. Kencke , Roksana Golizadeh Mojarad , Robert S. Chau
IPC分类号： H01L21/00 , H01L43/12 , H01L43/08 , H01L29/82 , H01L27/22 , H01L43/10 , H01F10/32 , H01F10/193 , G11C11/16
CPC分类号： H01L43/02 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/18 , H01F10/1933 , H01F10/3254 , H01F10/3286 , H01F41/325 , H01L27/226 , H01L27/228 , H01L29/82 , H01L43/08 , H01L43/10 , H01L43/12
摘要： Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
摘要翻译：适用于自旋转移转矩存储器（STTM）器件的磁隧道结（MTJ）包括垂直磁性层和通过结晶阻挡层与自由磁性层分离的一个或多个各向异性增强层。在实施方案中，各向异性增强层改善了自由磁性层的垂直取向，而结晶势垒改善了隧道磁阻（TMR）比，同时自由磁层的晶体结构与隧穿层的结构更好地对准。

3. 发明授权

US08836056B2 Perpendicular MTJ stacks with magnetic anisotropy enhancing layer and crystallization barrier layer 有权
标题翻译：具有磁各向异性增强层和结晶阻挡层的垂直MTJ叠层
公开(公告)号：US08836056B2
公开(公告)日：2014-09-16
申请号：US13627968
申请日：2012-09-26
申请人： Kaan Oguz , Mark L. Doczy , Brian Doyle , Uday Shah , David L. Kencke , Roksana Golizadeh Mojarad , Robert S. Chau
发明人： Kaan Oguz , Mark L. Doczy , Brian Doyle , Uday Shah , David L. Kencke , Roksana Golizadeh Mojarad , Robert S. Chau
IPC分类号： H01L29/32 , H01L43/12
CPC分类号： H01L43/02 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/18 , H01F10/1933 , H01F10/3254 , H01F10/3286 , H01F41/325 , H01L27/226 , H01L27/228 , H01L29/82 , H01L43/08 , H01L43/10 , H01L43/12
摘要： Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
摘要翻译：适用于自旋转移转矩存储器（STTM）器件的磁隧道结（MTJ）包括垂直磁性层和通过结晶阻挡层与自由磁性层分离的一个或多个各向异性增强层。在实施方案中，各向异性增强层改善了自由磁性层的垂直取向，而结晶势垒改善了隧道磁阻（TMR）比，同时自由磁层的晶体结构与隧穿层的结构更好地对准。

4. 发明申请

US20140095598A1 SYSTEMS, METHODS AND INTERFACES FOR EVALUATING AN ONLINE ENTITY PRESENCE 有权
标题翻译：用于评估在线实体存在的系统，方法和接口
公开(公告)号：US20140095598A1
公开(公告)日：2014-04-03
申请号：US13630035
申请日：2012-09-28
申请人： JILL SCHORNACK , Eric Iverson , Brian Doyle , Aaron Hareid
发明人： JILL SCHORNACK , Eric Iverson , Brian Doyle , Aaron Hareid
IPC分类号： H04L29/08
CPC分类号： H04L67/10 , G06Q10/06 , G06Q10/101 , G06Q50/01
摘要： A method for evaluating an online entity presence includes receiving a set of social media information for at least one entity and calculating a social media measurement where the social media measurement is associated with the set of social media information. The method further includes receiving a set of online profile information for the at least one entity, the set of online profile information being associated with one or more non-social media online profiles, and calculating an online profile measurement wherein the online profile measurement is associated with the set of online profile information. The method further includes calculating a reach value, the reach value being associated with the social media measurement and the online profile measurement and providing a reach score to a user where the reach score associated with the reach value.
摘要翻译：一种用于评估在线实体存在的方法包括：接收用于至少一个实体的一组社交媒体信息，并且计算社交媒体测量与所述一组社交媒体信息相关联的社交媒体测量。该方法还包括接收用于至少一个实体的一组在线简档信息，所述在线简档信息的集合与一个或多个非社交媒体在线简档相关联，以及计算在线简档测量，其中在线简档测量相关联与一组在线个人资料信息。该方法还包括计算一个达到值，该达到值与该社交媒体测量相关联，以及在线个人资料测量，并向该用户提供一个达到分数，该达成分与该达到值相关联。

5. 发明申请

US20130142450A1 REDUCING MOIRÉ PATTERNS 有权
标题翻译：减少运动模式
公开(公告)号：US20130142450A1
公开(公告)日：2013-06-06
申请号：US13309493
申请日：2011-12-01
申请人： Brian Doyle , Ralph Munsen , Eric Cole , James Bean
发明人： Brian Doyle , Ralph Munsen , Eric Cole , James Bean
IPC分类号： G06T5/00
CPC分类号： G06T5/002 , H04N1/40062 , H04N1/40068
摘要： Among other disclosed subject matter, a computer-implemented method includes receiving illustrated content. The illustrated content includes half-tone content. The method includes blurring at least part of the illustrated content. The blurring is performed according to a blur radius. The method includes downscaling the blurred illustrated content to an output size.
摘要翻译：在其他公开的主题中，计算机实现的方法包括接收所说明的内容。所示内容包括半色调内容。该方法包括模糊所示内容的至少一部分。模糊是根据模糊半径进行的。该方法包括将模糊的图示内容缩减为输出尺寸。

6. 发明授权

US08388854B2 Methods of forming nanodots using spacer patterning techniques and structures formed thereby 失效
标题翻译：使用间隔图案化技术和由此形成的结构形成纳米点的方法
公开(公告)号：US08388854B2
公开(公告)日：2013-03-05
申请号：US11968091
申请日：2007-12-31
申请人： Brian Doyle , Been-Yih Jin , Jack Kavalieros , Robert Chau
发明人： Brian Doyle , Been-Yih Jin , Jack Kavalieros , Robert Chau
IPC分类号： C23F1/00
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , Y10T428/24612
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first block on a nanodot material, forming a first spacer on the first block, removing the first block to form a free standing spacer, removing exposed portions of the nanodot material and then the free standing spacer to form nanowires, forming a second block at an angle to a length of the nanowires, forming a second spacer on the second block, forming a second free standing spacer on the nanowires by removing the second block, and removing exposed portions of the nanowires and then the second free standing spacer to form an ordered array of nanodots.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括在纳点物质上形成第一块，在第一块上形成第一间隔物，去除第一块以形成自由间隔物，去除纳米点材料的暴露部分，然后除去自由基间隔物以形成纳米线，在与所述纳米线的长度成一定角度地形成第二块，在所述第二块上形成第二间隔物，通过去除所述第二块在所述纳米线上形成第二自由间隔物，以及去除所述纳米线的暴露部分，然后除去所述第二自由基形成有序阵列的纳米点。

7. 发明授权

US08288233B2 Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned SI to SIGE conversion processes and structures formed thereby 有权
标题翻译：通过自对准SI将SIGNA转换过程和结构形成的多晶纳米级晶体管中的单轴应变的方法
公开(公告)号：US08288233B2
公开(公告)日：2012-10-16
申请号：US11864726
申请日：2007-09-28
申请人： Been-Yih Jin , Brian Doyle , Jack Kavalieros , Suman Datta
发明人： Been-Yih Jin , Brian Doyle , Jack Kavalieros , Suman Datta
IPC分类号： H01L21/8244
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7848
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the gate electrode, forming a silicon germanium layer on exposed portions of the top surface and the first and second laterally opposite sidewalls of the source drain region and then oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例可以包括提供包括顶表面和第一和第二横向相对的侧壁的栅电极，其中硬掩模设置在顶表面上，源极漏极区域设置在栅电极的相对侧上，在栅电极的第一和第二横向相对的侧壁上，在源漏区的顶表面和第一和第二横向相对的侧壁的暴露部分上形成硅锗层，然后氧化硅锗层的一部分，其中硅锗层的锗部分被迫下降到源极漏极区域中，以将源极区域的硅部分转换成源极漏极区域的硅锗部分。

8. 发明申请

US20120012934A1 NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION 有权
标题翻译：具有较薄体部分的非平面装置和制造方法
公开(公告)号：US20120012934A1
公开(公告)日：2012-01-19
申请号：US13243441
申请日：2011-09-23
申请人： Uday Shah , Brian Doyle , Justin K. Brask , Robert S. Chau , Thomas A. Letson
发明人： Uday Shah , Brian Doyle , Justin K. Brask , Robert S. Chau , Thomas A. Letson
IPC分类号： H01L29/78
CPC分类号： H01L29/42384 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/7856 , H01L2924/13067 , Y10S438/978
摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译：具有形成在基板的绝缘层上的半导体本体的非平面半导体器件。半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在顶表面处的横向相对侧壁之间的距离大于底表面处的距离。栅电介质层形成在半导体本体的顶表面和半导体本体的侧壁上。栅极电极形成在半导体本体的顶表面和侧壁上的栅介质层上。在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。

9. 发明申请

US20100155848A1 Trigate static random-access memory with independent source and drain engineering, and devices made therefrom 有权
标题翻译：调整静态随机存取存储器，具有独立的源和漏极工程，以及由此制造的器件
公开(公告)号：US20100155848A1
公开(公告)日：2010-06-24
申请号：US12317536
申请日：2008-12-24
申请人： Ravi Pillarisetty , Willy Rachmady , Brian Doyle , Robert S. Chau
发明人： Ravi Pillarisetty , Willy Rachmady , Brian Doyle , Robert S. Chau
IPC分类号： H01L29/66 , H01L21/8238
CPC分类号： H01L27/1104 , H01L21/823814 , H01L21/845 , H01L27/11 , H01L27/1211
摘要： A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (Rext) for the pull-down region to be lower than Rext for the pass region. Processes of achieving the static random-access memory circuit include source-and-drain epitaxy.
摘要翻译：静态随机存取存储器电路包括至少一个访问装置，其包括用于通过区域的源极和漏极部分，至少一个上拉装置和至少一个下拉装置，其包括用于下拉的源极和漏极部分地区。静态随机存取存储器电路被配置为用于下拉区域的外部电阻率（Rext）低于用于通过区域的Rext。实现静态随机存取存储器电路的过程包括源极和漏极外延。

10. 发明授权

US07666727B2 Semiconductor device having a laterally modulated gate workfunction and method of fabrication 失效
标题翻译：具有横向调制的栅极功能函数和制造方法的半导体器件
公开(公告)号：US07666727B2
公开(公告)日：2010-02-23
申请号：US11099190
申请日：2005-04-04
申请人： Brian Doyle , Scott A. Hareland , Mark Doczy , Robert S. Chau
发明人： Brian Doyle , Scott A. Hareland , Mark Doczy , Robert S. Chau
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L29/4983 , H01L21/28079 , H01L21/28088 , H01L21/28105 , H01L21/28194 , H01L21/28202 , H01L21/32051 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric layer and over the substrate region between the source and drain regions and a pair sidewall portions which overlap a portion of the source/drain regions wherein the central portion has a first work function and said pair of sidewall portions has a second work function, wherein the second work function is different than the first work function.
摘要翻译：一种晶体管，包括形成在形成于基板上的栅介质层上的栅电极。在栅电极的横向相对的侧壁的相对侧上的衬底中形成一对源极/漏极区域。栅极电极具有形成在栅极介电层上并且在源极和漏极区域之间的衬底区域上的中心部分和与源极/漏极区域的一部分重叠的一对侧壁部分，其中中心部分具有第一功函数和所述一对侧壁部分具有第二功函数，其中第二功函数不同于第一功函数。

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