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1. 发明申请

US20050251645A1 Method and apparatus for staggering execution of an instruction 有权
标题翻译：用于交错执行指令的方法和装置
公开(公告)号：US20050251645A1
公开(公告)日：2005-11-10
申请号：US11103702
申请日：2005-04-11
申请人： Patrice Roussel , Glenn Hinton , Shreekant Thakkar , Brent Boswell , Karol Menezes
发明人： Patrice Roussel , Glenn Hinton , Shreekant Thakkar , Brent Boswell , Karol Menezes
IPC分类号： G06F9/302 , G06F15/00
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
摘要翻译：公开了一种用于交错执行指令的方法和装置。根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。然后，使用相同电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素。第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。

2. 发明授权

US6055555A Interface for performing parallel arithmetic and round operations 失效
标题翻译：用于执行并行算术和循环操作的接口
公开(公告)号：US6055555A
公开(公告)日：2000-04-25
申请号：US999243
申请日：1997-12-29
申请人： Brent Boswell , Karol Menezes
发明人： Brent Boswell , Karol Menezes
IPC分类号： G06F7/52 , G06F7/523 , G06F7/57 , G06F7/38
CPC分类号： G06F7/483 , G06F7/49957 , G06F7/523
摘要： An interface circuit performs a last step of an arithmetic operation and a round operation in parallel. The interface circuit includes a first adder circuit that receives as an input a true result of an arithmetic operation in an intermediate format. The first adder circuit outputs both the true result in a final format and a first representable number approximating the true result. A second adder circuit is connected in parallel to the first adder circuit. The second adder circuit receives the true result in the intermediate format and a 1 as inputs. The second adder circuit outputs a second representable number approximating the true result. The interface circuit also includes a selection circuit connected to the outputs of the first and second adder circuits. The selection circuit outputs either the first or second representable numbers as a rounded result of the arithmetic operation.
摘要翻译：接口电路并行执行算术运算和循环运算的最后一步。接口电路包括第一加法器电路，其接收中间格式的算术运算的真实结果作为输入。第一加法器电路输出最终格式的真实结果和逼近真实结果的第一可表示数字。第二加法器电路并联连接到第一加法器电路。第二加法器电路以中间格式接收真实结果，将1作为输入。第二加法器电路输出接近真实结果的第二可表示数。接口电路还包括连接到第一和第二加法器电路的输出的选择电路。选择电路将第一或第二可表示数字输出为算术运算的舍入结果。

3. 发明申请

US20080082791A1 Providing temporary storage for contents of configuration registers 审中-公开
标题翻译：为配置寄存器的内容提供临时存储
公开(公告)号：US20080082791A1
公开(公告)日：2008-04-03
申请号：US11540337
申请日：2006-09-29
申请人： Srinivas Chennupaty , Avinash Sodani , Brent Boswell , Mark Seconi
发明人： Srinivas Chennupaty , Avinash Sodani , Brent Boswell , Mark Seconi
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30101 , G06F9/3824 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F9/462
摘要： In one embodiment, the present invention includes a method for assigning a first identifier to a first instruction that is to write control information into a configuration register, assigning the first identifier to a second instruction that is to read the control information written by the first instruction, and storing the second instruction in a first structure of a processor with the first identifier. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于将第一标识符分配给第一指令的方法，该第一指令将控制信息写入配置寄存器，将第一标识符分配给第二指令，该第二指令将读取由第一指令写入的控制信息并且将第二指令存储在具有第一标识符的处理器的第一结构中。描述和要求保护其他实施例。

4. 发明授权

US08189792B2 Method and apparatus for performing cryptographic operations 有权
标题翻译：用于执行加密操作的方法和装置
公开(公告)号：US08189792B2
公开(公告)日：2012-05-29
申请号：US12005680
申请日：2007-12-28
申请人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
发明人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
IPC分类号： G06F21/00
CPC分类号： H04L9/0631 , H04L2209/125
摘要： In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括处理器，其具有响应于第一和第二轮微操作执行一轮加密算法以在第一和第二列列上执行循环的逻辑，其中该逻辑包括半数的双数据通路加密算法宽度（或更小）的宽度。可以使用附加逻辑来组合第一和第二轮微操作的结果以获得圆形结果。描述和要求保护其他实施例。

5. 发明申请

US20090168999A1 Method and apparatus for performing cryptographic operations 有权
标题翻译：用于执行加密操作的方法和装置
公开(公告)号：US20090168999A1
公开(公告)日：2009-07-02
申请号：US12005680
申请日：2007-12-28
申请人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
发明人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
IPC分类号： H04L9/28 , H04L9/00
CPC分类号： H04L9/0631 , H04L2209/125
摘要： In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括处理器，其具有响应于第一和第二轮微操作执行一轮加密算法以在第一和第二列列上执行循环的逻辑，其中该逻辑包括半数的双数据通路加密算法宽度（或更小）的宽度。可以使用附加逻辑来组合第一和第二轮微操作的结果以获得圆形结果。描述和要求保护其他实施例。

6. 发明申请

US20090052659A1 METHOD AND APPARATUS FOR GENERATING AN ADVANCED ENCRYPTION STANDARD (AES) KEY SCHEDULE 有权
标题翻译：用于生成高级加密标准（AES）主要附表的方法和装置
公开(公告)号：US20090052659A1
公开(公告)日：2009-02-26
申请号：US11841556
申请日：2007-08-20
申请人： Shay Gueron , Martin G. Dixon , Srinivas Chennupaty , Mayank Bomb , Brent Boswell
发明人： Shay Gueron , Martin G. Dixon , Srinivas Chennupaty , Mayank Bomb , Brent Boswell
IPC分类号： H04L9/06
CPC分类号： H04L9/28 , G06F9/30007 , H04L9/0631 , H04L2209/125 , H04L2209/24
摘要： An Advanced Encryption Standard (AES) key generation assist instruction is provided. The AES key generation assist instruction assists in generating round keys used to perform AES encryption and decryption operations. The AES key generation instruction operates independent of the size of the cipher key and performs key generation operations in parallel on four 32-bit words thereby increasing the speed at which the round keys are generated. This instruction is easy to use in software. Hardware implementation of this instruction removes potential threats of software (cache access based) side channel attacks on this part of the AES algorithm.
摘要翻译：提供了高级加密标准（AES）密钥生成辅助指令。 AES密钥生成辅助指令有助于生成用于执行AES加密和解密操作的循环密钥。 AES密钥生成指令独立于密码密钥的大小，并行执行四个32位字的密钥生成操作，从而增加生成循环密钥的速度。该指令在软件中易于使用。该指令的硬件实现可以消除这部分AES算法对软件（基于缓存访问的）侧面信道攻击的潜在威胁。

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