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1. 发明授权

US08028924B2 Device and method for providing an integrated circuit with a unique identification 有权
标题翻译：用于为集成电路提供独特识别的装置和方法
公开(公告)号：US08028924B2
公开(公告)日：2011-10-04
申请号：US12560031
申请日：2009-09-15
申请人： Brent A. Anderson , Andres Bryant , Alain Loiseau , Anthony K. Stamper , Mickey H. Yu
发明人： Brent A. Anderson , Andres Bryant , Alain Loiseau , Anthony K. Stamper , Mickey H. Yu
IPC分类号： G06K19/06 , G06K19/00
CPC分类号： G06K19/067 , G06F21/73 , G06F2221/2129
摘要： A device and method for providing an integrated circuit with a unique identification. The device is usable on an integrated circuit (IC) for generating an identification (ID) identifying the IC and includes a plurality of identification cells each utilizing one of a four wire resistor, thin film resistors, and an inverter pair. A measurement circuit measures a parameter of each cell and is utilized in generating the ID in response thereto.
摘要翻译：一种用于向集成电路提供唯一标识的装置和方法。该装置可用于产生识别IC的识别（ID）的集成电路（IC），并且包括利用四线电阻器，薄膜电阻器和逆变器对之一的多个识别单元。测量电路测量每个单元的参数，并且用于响应于此生成ID。

2. 发明申请

US20090267156A1 DEVICE STRUCTURES INCLUDING DUAL-DEPTH TRENCH ISOLATION REGIONS AND DESIGN STRUCTURES FOR A STATIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：设备结构包括双深度分离隔离区域和静态随机访问存储器的设计结构
公开(公告)号：US20090267156A1
公开(公告)日：2009-10-29
申请号：US12111285
申请日：2008-04-29
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
IPC分类号： H01L27/092 , G06F17/50
CPC分类号： H01L21/823481 , H01L27/1104
摘要： Device structures and design structures for a static random access memory. The device structure includes a well of a first conductivity type in a semiconductor layer, first and second deep trench isolation regions in the semiconductor layer that laterally bound a device region in the well, and first and second pluralities of doped regions of a second conductivity type in the first device region. A shallow trench isolation region extends laterally across in the device region to connect the first and second deep trench isolation regions, and is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends from the top surface into the semiconductor layer to a first depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.
摘要翻译：静态随机存取存储器的器件结构和设计结构。器件结构包括在半导体层中的第一导电类型的阱，半导体层中的横向地限定阱中的器件区域的第一和第二深沟槽隔离区以及第二和第二多个第二导电类型的掺杂区在第一个设备区域。浅沟槽隔离区域在器件区域中横向延伸以连接第一和第二深沟槽隔离区域，并且设置在第一和第二多个掺杂区域之间的器件区域中。浅沟槽隔离区域从顶表面延伸到半导体层到第一深度，使得阱在浅沟槽隔离区域下连续。栅极堆叠控制一对第一多个掺杂区域之间的载流子流动。

3. 发明授权

US08536018B1 Maskless inter-well deep trench isolation structure and methods of manufacture 有权
标题翻译：无掩膜深沟槽隔离结构及制造方法
公开(公告)号：US08536018B1
公开(公告)日：2013-09-17
申请号：US13467314
申请日：2012-05-09
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
IPC分类号： H01L27/108
CPC分类号： H01L21/76283 , H01L21/76232 , H01L21/84
摘要： A low power maskless inter-well deep trench isolation structure and methods of manufacture such structure are provided. A method includes depositing a plurality of layers over a substrate, and forming a layer over the plurality of layers. The method also includes forming well structures in the substrate, and forming sidewall spacers at opposing sides of the layer. The method further includes forming a self-aligned deep trench in the substrate to below the well structures, by removing the sidewall spacers and portions of the substrate aligned with an opening formed by the removal of the sidewall spacers. The method also includes forming a shallow trench in alignment with the deep trench. The method further includes forming shallow trench isolation structures and deep trench isolation structures by filling the shallow trench and the deep trench with insulator material.
摘要翻译：提供了一种低功率无掩膜深沟槽隔离结构及其制造方法。一种方法包括在衬底上沉积多个层，并在多个层上形成层。该方法还包括在衬底中形成阱结构，以及在层的相对侧形成侧壁间隔物。该方法还包括通过去除侧壁间隔件和与通过去除侧壁间隔件形成的开口对准的衬底的部分，将衬底中的自对准深沟槽形成在阱结构下方。该方法还包括形成与深沟槽对准的浅沟槽。该方法还包括通过用绝缘体材料填充浅沟槽和深沟槽来形成浅沟槽隔离结构和深沟槽隔离结构。

4. 发明申请

US20090269897A1 METHODS OF FABRICATING DUAL-DEPTH TRENCH ISOLATION REGIONS FOR A MEMORY CELL 审中-公开
标题翻译：制备记忆细胞的双深度分离分离区的方法
公开(公告)号：US20090269897A1
公开(公告)日：2009-10-29
申请号：US12111266
申请日：2008-04-29
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
IPC分类号： H01L21/8234
CPC分类号： H01L21/823481 , H01L27/1104
摘要： Methods for fabricating dual-depth trench isolation regions for a memory cell. First and second deep trench isolation regions are formed in the semiconductor layer that laterally bound a device region in a well of a first conductivity type in the semiconductor layer. First and second pluralities of doped regions of a second conductivity type are formed in the device region. A shallow trench isolation region is formed that extends laterally across the device region from the first deep trench isolation region to the second deep trench isolation region. The shallow trench isolation region is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends into the semiconductor layer to a depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.
摘要翻译：用于制造用于存储单元的双深度沟槽隔离区域的方法。在半导体层中形成第一和第二深沟槽隔离区域，该半导体层横向地限定半导体层中的第一导电类型的阱中的器件区域。在器件区域中形成第二导电类型的第一和第二多个掺杂区域。形成了浅沟槽隔离区域，其横跨穿过器件区域从第一深沟槽隔离区域延伸到第二深沟槽隔离区域。浅沟槽隔离区设置在第一和第二多个掺杂区域之间的器件区域中。浅沟槽隔离区域延伸到半导体层中的深度，使得阱在浅沟槽隔离区域之下是连续的。栅极堆叠控制一对第一多个掺杂区域之间的载流子流动。

5. 发明授权

US07723178B2 Shallow and deep trench isolation structures in semiconductor integrated circuits 失效
标题翻译：半导体集成电路中浅沟槽和深沟槽隔离结构
公开(公告)号：US07723178B2
公开(公告)日：2010-05-25
申请号：US12175474
申请日：2008-07-18
申请人： James William Adkisson , Andres Bryant , Anthony Kendall Stamper , Mickey H. Yu
发明人： James William Adkisson , Andres Bryant , Anthony Kendall Stamper , Mickey H. Yu
IPC分类号： H01L21/8238
CPC分类号： H01L27/105 , H01L21/823481 , H01L21/823878
摘要： A semiconductor structure fabrication method. The method includes providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer. A second semiconductor layer on the first semiconductor layer is formed. The first and second semiconductor layers include a semiconductor material. A dielectric top portion and a first STI (Shallow Trench Isolation) region are formed in the second semiconductor layer. The dielectric top portion is in direct physical contact with the dielectric bottom portion.
摘要翻译：半导体结构制造方法。该方法包括提供在第一半导体层中包括第一半导体层和电介质底部的半导体结构。形成第一半导体层上的第二半导体层。第一和第二半导体层包括半导体材料。在第二半导体层中形成电介质顶部和第一STI（浅沟槽隔离）区域。电介质顶部与电介质底部部分直接物理接触。

6. 发明申请

US20100015765A1 SHALLOW AND DEEP TRENCH ISOLATION STRUCTURES IN SEMICONDUCTOR INTEGRATED CIRCUITS 失效
标题翻译：半导体集成电路中的深度和深度分离分离结构
公开(公告)号：US20100015765A1
公开(公告)日：2010-01-21
申请号：US12175474
申请日：2008-07-18
申请人： James William Adkisson , Andres Bryant , Anthony Kendall Stamper , Mickey H. Yu
发明人： James William Adkisson , Andres Bryant , Anthony Kendall Stamper , Mickey H. Yu
IPC分类号： H01L21/8238
CPC分类号： H01L27/105 , H01L21/823481 , H01L21/823878
摘要： A semiconductor structure fabrication method. The method includes providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer. A second semiconductor layer on the first semiconductor layer is formed. The first and second semiconductor layers include a semiconductor material. A dielectric top portion and a first STI (Shallow Trench Isolation) region are formed in the second semiconductor layer. The dielectric top portion is in direct physical contact with the dielectric bottom portion.
摘要翻译：半导体结构制造方法。该方法包括提供在第一半导体层中包括第一半导体层和电介质底部的半导体结构。形成第一半导体层上的第二半导体层。第一和第二半导体层包括半导体材料。在第二半导体层中形成电介质顶部和第一STI（浅沟槽隔离）区域。电介质顶部与电介质底部部分直接物理接触。

7. 发明授权

US6121064A STI fill for SOI which makes SOI inspectable 失效
标题翻译： STI填充SOI，可以对SOI进行检查
公开(公告)号：US6121064A
公开(公告)日：2000-09-19
申请号：US224826
申请日：1999-01-04
申请人： Jerome B. Lasky , Bret Philips , Anthony C. Speranza , Justin Wong , Mickey H. Yu
发明人： Jerome B. Lasky , Bret Philips , Anthony C. Speranza , Justin Wong , Mickey H. Yu
IPC分类号： H01L21/66
CPC分类号： H01L22/24
摘要： A method of manufacturing and inspecting SOI such that during STI formation, by depositing a light absorbing layer in the STI such as hydrosilicon oxynitride, the silicon inclusions in the buried insulator layer of the SOI are undetectable by an optical inspection. The reduction in background effects allows for improved optical inspection of SOI wafers without having to discriminate against defects created by SOI formation. A method of manufacturing and inspecting semiconductor devices is disclosed wherein deposition of a light absorbing layer, such as hydrosilicon oxynitride, prevents defects occurring prior to deposition from being optically inspectable and those defects created during the most recent processing can be easily distinguished. Also disclosed are an optically inspectable semiconductor device and an optically inspectable semiconductor device having an STI.
摘要翻译：制造和检查SOI的方法，使得在STI形成期间，通过在诸如氢氧化硅氮氧化物的STI中沉积光吸收层，SOI的掩埋绝缘体层中的硅夹杂物通过光学检查是不可检测的。背景效应的降低允许改进SOI晶片的光学检查，而不必区分由SOI形成产生的缺陷。公开了制造和检查半导体器件的方法，其中诸如氢氧化硅氮氧化物的光吸收层的沉积防止在沉积之前发生的缺陷被光学检查，并且可以容易地区分在最近的处理期间产生的那些缺陷。还公开了具有STI的可光学检查的半导体器件和可光学检查的半导体器件。

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