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1. 发明授权

US07606981B2 System and method for reducing store latency 有权
标题翻译：减少存储延迟的系统和方法
公开(公告)号：US07606981B2
公开(公告)日：2009-10-20
申请号：US11311751
申请日：2005-12-19
申请人： Bratin Saha , Hariharan L. Thantry , Ali-Reza Adl-Tabatabai
发明人： Bratin Saha , Hariharan L. Thantry , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00
CPC分类号： G06F12/0822
摘要： According to one embodiment of the invention, a method comprises verifying that a cache block is not exclusively owned, and if not, transmitting a message identifying both the cache block and a caching agent requesting ownership of the cache block to a broadcast interconnect.
摘要翻译：根据本发明的一个实施例，一种方法包括验证高速缓存块不是专有的，如果没有，则将识别高速缓存块和缓存代理的高速缓存代理的消息发送到广播互连。

2. 发明授权

US09152419B2 Instruction set for supporting wide scalar pattern matches 有权
标题翻译：支持宽标量模式匹配的指令集
公开(公告)号：US09152419B2
公开(公告)日：2015-10-06
申请号：US13718816
申请日：2012-12-18
申请人： Hariharan L. Thantry , Mani Azimi
发明人： Hariharan L. Thantry , Mani Azimi
IPC分类号： G06F9/00 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30036
摘要： A processor includes an instruction decoder to receive an instruction having a first operand, a second operand, and a third operand, and an execution unit coupled to the instruction decoder to execute the instruction, the execution unit to individually perform a shift operation by at least one bit for each of a plurality of data elements stored in a storage location indicated by the second operand, for each of the data elements that has an overflow in response to the shift-left operation, to carry over the overflow into an adjacent data element based on a first bitmask obtained from the third operand, generating a final result, and to store the final result in a storage location indicated by the first operand.
摘要翻译：处理器包括：指令解码器，用于接收具有第一操作数，第二操作数和第三操作数的指令;以及执行单元，耦合到指令解码器以执行指令，执行单元至少单独执行移位操作对于响应于左移操作而具有溢出的每个数据元素，存储在由第二操作数指示的存储位置中的多个数据元素中的每一个的一位用于将溢出传送到相邻数据元素基于从第三操作数获得的第一位掩码，生成最终结果，并将最终结果存储在由第一操作数指示的存储位置中。

3. 发明申请

US20140173255A1 INSTRUCTION SET FOR SUPPORTING WIDE SCALAR PATTERN MATCHES 有权
标题翻译：用于支持宽标度图案匹配的指令集
公开(公告)号：US20140173255A1
公开(公告)日：2014-06-19
申请号：US13718816
申请日：2012-12-18
申请人： Hariharan L. Thantry , Mani Azimi
发明人： Hariharan L. Thantry , Mani Azimi
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30036
摘要： A processor includes an instruction decoder to receive an instruction having a first operand, a second operand, and a third operand, and an execution unit coupled to the instruction decoder to execute the instruction, the execution unit to individually perform a shift operation by at least one bit for each of a plurality of data elements stored in a storage location indicated by the second operand, for each of the data elements that has an overflow in response to the shift-left operation, to carry over the overflow into an adjacent data element based on a first bitmask obtained from the third operand, generating a final result, and to store the final result in a storage location indicated by the first operand.
摘要翻译：处理器包括：指令解码器，用于接收具有第一操作数，第二操作数和第三操作数的指令;以及执行单元，耦合到指令解码器以执行指令，执行单元至少单独执行移位操作对于响应于左移操作而具有溢出的每个数据元素，存储在由第二操作数指示的存储位置中的多个数据元素中的每一个的一位用于将溢出传送到相邻数据元素基于从第三操作数获得的第一位掩码，生成最终结果，并将最终结果存储在由第一操作数指示的存储位置中。

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