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1. 发明申请

US20070232014A1 Method of fabricating a planar MIM capacitor 审中-公开
标题翻译：制造平面MIM电容器的方法
公开(公告)号：US20070232014A1
公开(公告)日：2007-10-04
申请号：US11396844
申请日：2006-04-03
申请人： Bradley Larsen , Jerry Yue
发明人： Bradley Larsen , Jerry Yue
IPC分类号： H01L21/20
CPC分类号： H01L28/40
摘要： A method of fabricating a Metal-Insulator-Metal (MIM) capacitor is presented. The method includes depositing a bottom plate of the MIM capacitor on a passivating dielectric layer which may be a pre-metal or post metal dielectric layer. A capacitor dielectric of the MIM capacitor is subsequently deposited on top of the bottom plate. The capacitor dielectric and the bottom plate both conform to the profile of the passivating dielectric layer. In addition, because the bottom plate is located on a dielectric, which is thermally stable and does not morph or change significantly with successive thermal processing, the capacitor dielectric does not have to be designed to compensate for topography changes due to such thermal processing.
摘要翻译：提出了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。该方法包括将MIM电容器的底板沉积在钝化介质层上，钝化介电层可以是金属前金属或后金属介电层。 MIM电容器的电容电介质随后沉积在底板的顶部上。电容器电介质和底板都符合钝化介电层的轮廓。另外，由于底板位于电介质上，其是热稳定的并且不会随着连续热处理而变形或显着变化，所以电容器电介质不必被设计成补偿由于这种热处理而引起的形貌变化。

2. 发明申请

US20050207691A1 Silicon-insulator-silicon thin-film structures for optical modulators and methods of manufacture 失效
标题翻译：用于光学调制器的硅绝缘体 - 硅薄膜结构和制造方法
公开(公告)号：US20050207691A1
公开(公告)日：2005-09-22
申请号：US10915299
申请日：2004-08-10
申请人： Thomas Keyser , Cheisan Yue , Bradley Larsen
发明人： Thomas Keyser , Cheisan Yue , Bradley Larsen
IPC分类号： G02F1/01 , G02F1/025 , H01L21/77
CPC分类号： G02B6/132 , G02B6/131 , G02F1/025
摘要： The present invention provides silicon based thin-film structures that can be used to form high frequency optical modulators. Devices of the invention are formed as layered structures that have a thin-film dielectric layer, such as silicon dioxide, sandwiched between silicon layers. The silicon layers have high free carrier mobility. In one aspect of the invention a high mobility silicon layer can be provided by crystallizing an amorphous silicon layer. In another aspect of the invention, a high mobility silicon layer can be provided by using selective epitaxial growth and extended lateral overgrowth thereof.
摘要翻译：本发明提供了可用于形成高频光学调制器的硅基薄膜结构。本发明的器件形成为具有夹在硅层之间的诸如二氧化硅的薄膜电介质层的分层结构。硅层具有高自由载流子迁移率。在本发明的一个方面，可以通过使非晶硅层结晶来提供高迁移率硅层。在本发明的另一方面，通过使用选择性外延生长和其延伸的横向过度生长，可以提供高迁移率硅层。

3. 发明申请

US20070045710A1 Single-poly EEPROM cell with lightly doped MOS capacitors 有权
标题翻译：具有轻掺杂MOS电容器的单多晶硅EEPROM单元
公开(公告)号：US20070045710A1
公开(公告)日：2007-03-01
申请号：US11217829
申请日：2005-09-01
申请人： James Riekels , Thomas Lucking , Bradley Larsen , Gary Gardner
发明人： James Riekels , Thomas Lucking , Bradley Larsen , Gary Gardner
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L27/1203
摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. The lightly doped capacitors employed in the EEPROM memory cell can be asymmetrical in design. Asymmetrical capacitors reduce area. Further capacitance variation caused by inversion can also be reduced by using multiple control capacitors. In addition, the use of multiple tunneling capacitors provides the benefit of customized tunneling paths.
摘要翻译：公开了电可擦除可编程只读存储器（EEPROM）存储单元和操作方法，用于在标准CMOS工艺中创建EEPROM存储器单元。单个多晶硅层与轻掺杂的MOS电容器结合使用。在EEPROM存储单元中使用的轻掺杂电容器在设计中可以是不对称的。不对称电容器减少面积。通过使用多个控制电容器也可以减少由反转引起的进一步的电容变化。此外，使用多个隧道电容器可提供定制的隧道路径的优点。

4. 发明申请

US20100019320A1 Direct Contact to Area Efficient Body Tie Process Flow 失效
标题翻译：直接接触面积有效的身体贴身过程流程
公开(公告)号：US20100019320A1
公开(公告)日：2010-01-28
申请号：US12177332
申请日：2008-07-22
申请人： Paul Fechner , Bradley Larsen , Gregor Dougal , Keith Golke
发明人： Paul Fechner , Bradley Larsen , Gregor Dougal , Keith Golke
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L21/84 , H01L29/66772 , H01L29/78615
摘要： A process flow for fabricating shallow trench isolation (STI) devices with direct body tie contacts is provided. The process flow follows steps similar to standard STI fabrication methods except that in one of the etching steps, body tie contacts are etched through the nitride layer and STI oxide layer, directly to the body tie. This process flow provides a direct body tie contact to mitigate floating body effects but also eliminates hysteresis and transient upset effects common in non-direct body tie contact configurations, without the critical alignment requirements and critical dimension control of the layout.
摘要翻译：提供了一种用于制造具有直接身体接头的浅沟槽隔离（STI）装置的工艺流程。工艺流程遵循类似于标准STI制造方法的步骤，除了在其中一个蚀刻步骤中，通过氮化物层和STI氧化物层直接将身体接头触点蚀刻到身体接合处。该过程流程提供了直接的身体接触以减轻浮体效应，但也消除了非直接身体接头接触配置中常见的滞后和瞬态扰动效应，而不需要布局的关键对准要求和关键尺寸控制。

5. 发明授权

US07964897B2 Direct contact to area efficient body tie process flow 失效
标题翻译：直接接触区域有效的身体扎扎过程流程
公开(公告)号：US07964897B2
公开(公告)日：2011-06-21
申请号：US12177332
申请日：2008-07-22
申请人： Paul S. Fechner , Bradley Larsen , Gregor Dougal , Keith Golke
发明人： Paul S. Fechner , Bradley Larsen , Gregor Dougal , Keith Golke
IPC分类号： H01L29/76 , H01L21/335
CPC分类号： H01L21/84 , H01L29/66772 , H01L29/78615
摘要： A process flow for fabricating shallow trench isolation (STI) devices with direct body tie contacts is provided. The process flow follows steps similar to standard STI fabrication methods except that in one of the etching steps, body tie contacts are etched through the nitride layer and STI oxide layer, directly to the body tie. This process flow provides a direct body tie contact to mitigate floating body effects but also eliminates hysteresis and transient upset effects common in non-direct body tie contact configurations, without the critical alignment requirements and critical dimension control of the layout.
摘要翻译：提供了一种用于制造具有直接身体接头的浅沟槽隔离（STI）装置的工艺流程。工艺流程遵循类似于标准STI制造方法的步骤，除了在其中一个蚀刻步骤中，通过氮化物层和STI氧化物层直接将身体接头触点蚀刻到身体接合处。该过程流程提供了直接的身体接触以减轻浮体效应，但也消除了非直接身体接头接触配置中常见的滞后和瞬态扰动效应，而不需要布局的关键对准要求和关键尺寸控制。

6. 发明申请

US20060186509A1 Shallow trench isolation structure with active edge isolation 审中-公开
标题翻译：浅沟隔离结构，主动边缘隔离
公开(公告)号：US20060186509A1
公开(公告)日：2006-08-24
申请号：US11064556
申请日：2005-02-24
申请人： Bradley Larsen
发明人： Bradley Larsen
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/76283 , H01L21/3086 , H01L21/76232 , H01L29/0649
摘要： A method of fabricating a shallow trench isolation (STI) structure with active edge isolation and increased radiation hardening is presented. The invention comprises forming a pad oxide layer on a substrate. Then a masking layer is formed on the pad oxide and is patterned to define the STI structure trench and spacer locations. A conformal layer of oxide is deposited and is formed into oxide spacers which extend over the active edge of the substrate. The STI structure trench is then etched and a liner oxide is formed on the walls of the trench. The trench is then filled with a dielectric material to form a central oxide region. The central oxide region and oxide spacers are then etched to a desired height and planarized. Finally, the masking layer and portions of the pad oxide layer are then removed.
摘要翻译：提出了一种制造具有主动边缘隔离和增加辐射硬化的浅沟槽隔离（STI）结构的方法。本发明包括在衬底上形成衬垫氧化物层。然后在衬垫氧化物上形成掩模层，并对其进行构图以限定STI结构沟槽和间隔物位置。沉积保形层的氧化物，并形成为在衬底的有效边缘上延伸的氧化物间隔物。然后蚀刻STI结构沟槽，并且在沟槽的壁上形成衬垫氧化物。然后用电介质材料填充沟槽以形成中心氧化物区域。然后将中心氧化物区域和氧化物间隔物蚀刻到期望的高度并且被平坦化。最后，去除掩模层和焊盘氧化物层的部分。

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