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1. 发明授权

US5812839A Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit 失效
标题翻译：双预测分支系统具有分支恢复过程的两个步骤，仅在错误预测分支是无序单元中最旧的指令时激活
公开(公告)号：US5812839A
公开(公告)日：1998-09-22
申请号：US851141
申请日：1997-05-05
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3844 , G06F9/3863 , G06F9/3885
摘要： A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.
摘要翻译：公开了一种用于流水线处理器的四级分支指令解析系统。分支指令解析系统的第一阶段预测指令流内分支指令的存在和结果，使得指令获取单元可以连续地获取指令。第二阶段解码所有提取的指令。如果解码级确定由第一级预测的分支指令不是分支指令，则解码级别刷新流水线并以校正的地址重新启动处理器。解码阶段验证分支预测阶段所做的所有分支预测。最后，解码阶段对分支预测阶段未预测的分支进行分支预测。第三阶段执行所有分支指令以确定最终分支结果和最终分支目标地址。分支执行阶段将最终分支结果和最终分支目标地址与预测的分支结果和预测分支目标地址进行比较，以确定处理器是否必须冲洗微处理器流水线的前端并以修正的地址重新启动。最终的分支解决阶段退出所有分支指令。退休阶段确保在错误预测的分支之后提取的任何指令不会被永久保留。

2. 发明授权

US5768576A Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor 失效
标题翻译：用于预测和处理计算机处理器中的子程序指令的解析返回的方法和装置
公开(公告)号：US5768576A
公开(公告)日：1998-06-16
申请号：US739743
申请日：1996-10-29
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4426
摘要： A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the instruction stream. The first stage stores a return address in a return register when a Call Subroutine instruction is predicted. The first stage predicts a return to the return address in the return register when a Return From Subroutine instruction is predicted. A second stage decodes each Call Subroutine and Return From Subroutine instruction in order to maintain a Return Stack Buffer that stores a stack of return addresses. Each time the second stage decodes a Call Subroutine instruction, a return address is pushed onto the Return Stack Buffer. Correspondingly, each time the second stage decodes a Return From Subroutine instruction, a return address is popped off of the Return Stack Buffer. The second stage verifies predictions made by the first stage and predicts return addresses for Return From Subroutine instructions that were not predicted by the first stage. A third stage executes Return From Subroutine instructions such that the predictions are verified. Finally, a fourth stage retires Return From Subroutine instructions and ensures that no instructions fetch after a mispredicted return address are committed into permanent state.
摘要翻译：公开了一种用于解决计算机处理器中的子程序返回指令的方法和装置。该方法和设备分四个阶段解析子程序指令。第一阶段预测指令流中的调用子程序指令和子程序返回指令。当预测一个调用子程序指令时，第一阶段将返回地址存储在一个返回寄存器中。第一阶段预测当返回从子程序指令被预测时返回寄存器中的返回地址。第二阶段解码每个调用子程序和从子程序返回指令，以便维护一个存储一堆返回地址的返回栈缓冲区。每次第二阶段解码一个调用子程序指令时，一个返回地址被推到返回栈缓冲区上。相应地，每次第二级解码从子程序返回指令时，返回地址从返回堆栈缓冲区中弹出。第二阶段验证第一阶段做出的预测，并预测第一阶段未预测的返回从子程序指令的返回地址。第三阶段执行从子程序返回指令，使得预测得到验证。最后，第四阶段退出从子程序返回指令，并确保在错误预测的返回地址之后没有指令提取到永久状态。

3. 发明授权

US5903751A Method and apparatus for implementing a branch target buffer in CISC processor 失效
标题翻译：在CISC处理器中实现分支目标缓冲器的方法和装置
公开(公告)号：US5903751A
公开(公告)日：1999-05-11
申请号：US931807
申请日：1997-09-16
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.
摘要翻译：公开了一种使用计算机指令流预测分支指令的计算机处理器中的分支目标缓冲器电路。分支目标缓冲器电路使用分支目标缓冲器高速缓存，其存储关于先前执行的分支指令的分支信息。存储在分支目标缓冲区高速缓存中的分支信息由每个分支指令的最后一个字节寻址。当计算机处理器中的指令获取单元获取指令块时，它向分支目标缓冲器电路发送指令指针。基于指令指针，分支目标缓冲器电路查找分支目标缓冲区高速缓存以查看正在获取的块中的任何指令是否是分支指令。当分支目标缓冲器电路在分支目标缓冲器高速缓存中找到即将到来的分支指令时，分支目标缓冲器电路通知指令获取单元关于即将到来的分支指令。

4. 发明授权

US5706492A Method and apparatus for implementing a set-associative branch target buffer 失效
公开(公告)号：US5706492A
公开(公告)日：1998-01-06
申请号：US687975
申请日：1996-07-29
申请人： Bradley D. Hoyt , Glenn I. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn I. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

5. 发明授权

US5944817A Method and apparatus for implementing a set-associative branch target buffer 有权
标题翻译：用于实现集合关联分支目标缓冲器的方法和装置
公开(公告)号：US5944817A
公开(公告)日：1999-08-31
申请号：US168305
申请日：1998-10-07
申请人： Bradley D. Hoyt , Glenn I. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn I. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.
摘要翻译：公开了一种使用计算机指令流预测分支指令的计算机处理器中的分支目标缓冲器电路。分支目标缓冲器电路使用分支目标缓冲器高速缓存，其存储关于先前执行的分支指令的分支信息。存储在分支目标缓冲区高速缓存中的分支信息由每个分支指令的最后一个字节寻址。当计算机处理器中的指令获取单元获取指令块时，它向分支目标缓冲器电路发送指令指针。基于指令指针，分支目标缓冲器电路查找分支目标缓冲区高速缓存以查看正在获取的块中的任何指令是否是分支指令。当分支目标缓冲器电路在分支目标缓冲器高速缓存中找到即将到来的分支指令时，分支目标缓冲器电路通知指令获取单元关于即将到来的分支指令。

6. 发明授权

US5604877A Method and apparatus for resolving return from subroutine instructions in a computer processor 失效
标题翻译：用于解决计算机处理器中子程序指令返回的方法和装置
公开(公告)号：US5604877A
公开(公告)日：1997-02-18
申请号：US176065
申请日：1994-01-04
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4426
摘要： A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the instruction stream. The first stage stores a return address in a return register when a Call Subroutine instruction is predicted. The first stage predicts a return to the return address in the return register when a Return From Subroutine instruction is predicted. A second stage decodes each Call Subroutine and Return From Subroutine instruction in order to maintain a Return Stack Buffer that stores a stack of return addresses. Each time the second stage decodes a Call Subroutine instruction, a return address is pushed onto the Return Stack Buffer. Correspondingly, each time the second stage decodes a Return From Subroutine instruction, a return address is popped off of the Return Stack Buffer. The second stage verifies predictions made by the first stage and predicts return addresses for Return From Subroutine instructions that were not predicted by the first stage. A third stage executes Return From Subroutine instructions such that the predictions are verified. Finally, a fourth stage retires Return From Subroutine instructions and ensures that no instructions fetch after a mispredicted return address are committed into permanent state.
摘要翻译：公开了一种用于解决计算机处理器中的子程序返回指令的方法和装置。该方法和设备分四个阶段解析子程序指令。第一阶段预测指令流中的调用子程序指令和子程序返回指令。当预测一个调用子程序指令时，第一阶段将返回地址存储在一个返回寄存器中。第一阶段预测当返回从子程序指令被预测时返回寄存器中的返回地址。第二阶段解码每个调用子程序和从子程序返回指令，以便维护一个存储一堆返回地址的返回栈缓冲区。每次第二阶段解码一个调用子程序指令时，一个返回地址被推到返回栈缓冲区上。相应地，每次第二级解码从子程序返回指令时，返回地址从返回堆栈缓冲区中弹出。第二阶段验证第一阶段做出的预测，并预测第一阶段未预测的返回从子程序指令的返回地址。第三阶段执行从子程序返回指令，使得预测得到验证。最后，第四阶段退出从子程序返回指令，并确保在错误预测的返回地址之后没有指令提取到永久状态。

7. 发明授权

US5574871A Method and apparatus for implementing a set-associative branch target buffer 失效
公开(公告)号：US5574871A
公开(公告)日：1996-11-12
申请号：US177155
申请日：1994-01-04
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

8. 发明授权

US5918046A Method and apparatus for a branch instruction pointer table 失效
标题翻译：分支指令指针表的方法和装置
公开(公告)号：US5918046A
公开(公告)日：1999-06-29
申请号：US783073
申请日：1997-01-15
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Subramanian Natarajan , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Subramanian Natarajan , Reynold V. D'Sa
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/322 , G06F9/3861
摘要： A buffer is used to store information about the branch instructions within a pipelined microprocessor that can speculatively execute instructions. When a branch instruction in the microprocessor is decoded, the address of the instruction immediately following the branch instruction (the Next Linear Instruction Pointer or NLIP) and some processor state information is written into a Branch Instruction Pointer Table. The branch instruction then proceeds down the microprocessor pipeline. Eventually, the branch instruction is executed. The resolved branch outcome for the branch instruction is compared with a predicted branch outcome. If the branch prediction was correct, the microprocessor continues execution along the current path. However, if the branch prediction was wrong then the execution unit flushes the front-end microprocessor pipeline and restores the microprocessor state information that was stored in the Branch IP Table. If the branch was mispredicted as not taken, the execution unit instructs an Instruction Fetch Unit to resume execution at a final branch target address. Alternatively, if the branch was mispredicted as taken when the branch should not have been taken, the execution unit instructs the Instruction Fetch Unit to resume execution at the Next Linear Instruction Pointer (NLIP) address stored in the Branch IP Table.
摘要翻译：缓冲器用于存储可以推测性地执行指令的流水线微处理器内关于分支指令的信息。当微处理器中的分支指令被解码时，紧跟在分支指令（下一个线性指令指针或NLIP）之后的指令的地址和一些处理器状态信息被写入分支指令指针表。然后分支指令继续沿着微处理器管线。最终执行分支指令。将分支指令的分解结果与预测的分支结果进行比较。如果分支预测是正确的，则微处理器沿着当前路径继续执行。然而，如果分支预测错误，则执行单元刷新前端微处理器流水线并恢复存储在分支IP表中的微处理器状态信息。如果分支被错误预测为未被执行，则执行单元指示指令获取单元在最终分支目标地址处恢复执行。或者，如果在不支持分支时分支被错误预测，则执行单元指示指令获取单元在存储在分支IP表中的下一个线性指令指针（NLIP）地址处继续执行。

9. 发明授权

US5778407A Methods and apparatus for determining operating characteristics of a memory element based on its physical location 失效
标题翻译：基于其物理位置来确定存储元件的操作特性的方法和装置
公开(公告)号：US5778407A
公开(公告)日：1998-07-07
申请号：US667241
申请日：1996-06-21
申请人： Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Michael Alan Fetterman , Robert P. Colwell , Frederick Jay Pollack
发明人： Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Michael Alan Fetterman , Robert P. Colwell , Frederick Jay Pollack
IPC分类号： G06F12/08 , G06F12/10 , G06F12/06
CPC分类号： G06F12/0888 , G06F12/1027 , G06F2212/206
摘要： A circuit comprising a number of range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory operating characteristics to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type, and the memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.
摘要翻译：包括多个范围寄存器和互补解码/匹配电路的电路被提供给处理器，用于确定物理地址的存储器类型，由此一旦物理地址在前面的执行阶段可用就允许确定存储器操作特性缓存访问。此外，存储器类型字段被提供给用于存储确定的存储器类型的数据和指令存储器子系统的每个地址转换后备缓冲器条目，并且存储器类型确定电路被布置在页面未命中处理器中，从而允许确定存储器类型同时确定物理地址。

10. 发明授权

US5913050A Method and apparatus for providing address-size backward compatibility in a processor using segmented memory 失效
标题翻译：在使用分段存储器的处理器中提供地址大小向后兼容性的方法和装置
公开(公告)号：US5913050A
公开(公告)日：1999-06-15
申请号：US735048
申请日：1996-10-22
申请人： Darrell D. Boggs , Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
发明人： Darrell D. Boggs , Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
IPC分类号： G06F9/32 , G06F9/38 , G06F12/06 , G06F9/26
CPC分类号： G06F9/3804 , G06F9/30054
摘要： This invention overcomes the address size backward compatibility problem by first subtracting the segment base address from the linear destination address of a branch instruction to generate a virtual destination address. It is assumed that the branch instruction destination address is n bits long with m most significant bits. It is desired to provide backward compatibility in the n-bit processor for branch instruction code written for processors utilizing instruction address fields of size (n-m) bits. After obtaining the virtual address, if any of the m most significant bits are non-zero, then those m bits are set to zero to thereby generate a corrected virtual address. If such a compatibility correction is necessary, then a clear signal is asserted to flush all state of the processor that resulted from instructions being fetched after the branch instruction was fetched. The corrected virtual address is added back to the segment base address to generate a corrected linear address. The next instruction is fetched at the corrected linear address.
摘要翻译：本发明通过首先从分支指令的线性目的地地址中减去分段基地址来生成虚拟目的地地址来克服地址大小向后兼容性问题。假设分支指令目标地址是n位长，m个最高有效位。期望在n比特处理器中为使用大小（n-m）比特的指令地址字段为处理器编写的分支指令代码提供向后兼容性。在获得虚拟地址之后，如果m个最高有效位中的任何一个非零，则将这些m位设置为零，从而生成校正的虚拟地址。如果需要这种兼容性校正，则清除信号被断言以清除在分支指令被取出之后被取出的指令导致的处理器的所有状态。校正的虚拟地址被加回到段基地址以产生校正的线性地址。下一条指令是在校正的线性地址处获取的。

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