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1. 发明申请

US20050154949A1 System for flexible embedded Boundary Scan testing 有权
标题翻译：灵活嵌入式边界扫描测试系统
公开(公告)号：US20050154949A1
公开(公告)日：2005-07-14
申请号：US10756689
申请日：2004-01-12
申请人： Bradford Van Treuren , Jose Miranda , Paul Wheatley
发明人： Bradford Van Treuren , Jose Miranda , Paul Wheatley
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318544 , G01R31/318555
摘要： A flexible Boundary Scan test system is disclosed. The system includes an interpreter module operable to execute a program element selected from a plurality of program elements that include at least one instruction type having an interface to identify and execute selected functions wherein each of the selected functions has associated therewith at least one data information item. In one aspect of the invention, selected ones of the functions are composed of a plurality of functions. In another aspect of the invention, the instruction includes parameters and adornments for determining the selected function execution.
摘要翻译：公开了一种灵活的边界扫描测试系统。该系统包括解释器模块，其可操作以执行从多个程序单元中选择的程序单元，所述程序单元包括至少一个指令类型，该指令类型具有用于识别和执行选定功能的接口，其中所选择的功能中的每一个与其相关联，至少一个数据信息项。在本发明的一个方面中，所选择的功能由多个功能组成。在本发明的另一方面，该指令包括用于确定所选功能执行的参数和装饰。

2. 发明申请

US20070069737A1 System and method for adaptable testing of backplane interconnections and a test tool incorporating the same 有权
公开(公告)号：US20070069737A1
公开(公告)日：2007-03-29
申请号：US11237083
申请日：2005-09-28
申请人： Bradford Van Treuren , Paul Wheatley
发明人： Bradford Van Treuren , Paul Wheatley
IPC分类号： G01R31/04
CPC分类号： G01R31/043
摘要： The present invention provides a system for, and method of, adaptable testing of backplane interconnections. In one embodiment, the system includes a board detector configured to determine a relative arrangement of a plurality of hardware boards populating positions associated with the backplane interconnections. Additionally, the system also includes a test coordinator coupled to the board detector and configured to adaptively backplane test at least a pair of the plurality of hardware boards based on the relative arrangement.

3. 发明申请

US20100229058A1 METHOD AND APPARATUS FOR SYSTEM TESTING USING SCAN CHAIN DECOMPOSITION 审中-公开
标题翻译：使用扫描链分解的系统测试的方法和装置
公开(公告)号：US20100229058A1
公开(公告)日：2010-09-09
申请号：US12495336
申请日：2009-06-30
申请人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
发明人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318558
摘要： A method is provided for testing a portion of a system under test via a scan chain of the system under test. The method includes decomposing the scan chain into a plurality of segments, generating a set of instructions for testing the portion of the system under test, and executing the set of instructions for testing the portion of the system under test. The scan chain is composed of a plurality of elements, and each segment includes at least one of the elements of the scan chain. The set of instructions includes a plurality of processor instructions associated with an Instruction Set Architecture (ISA), and a plurality of test instructions. The test instructions include, for each of the plurality of segments of the scan chain, at least one scan operation to be performed on the segment. An associated apparatus also is provided.
摘要翻译：提供了一种用于通过被测系统的扫描链测试待测系统的一部分的方法。该方法包括将扫描链分解成多个段，产生一组用于测试被测系统的部分的指令，以及执行用于测试被测系统部分的一组指令。扫描链由多个元件组成，并且每个片段包括扫描链的元件中的至少一个元件。所述指令集包括与指令集架构（ISA）相关联的多个处理器指令以及多个测试指令。对于扫描链的多个片段中的每一个，测试指令包括要在片段上执行的至少一个扫描操作。还提供了一种相关联的装置。

4. 发明申请

US20100293423A1 METHOD AND APPARATUS FOR VIRTUAL IN-CIRCUIT EMULATION 有权
标题翻译：虚拟电路仿真的方法和装置
公开(公告)号：US20100293423A1
公开(公告)日：2010-11-18
申请号：US12827556
申请日：2010-06-30
申请人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
发明人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/3177 , G01R31/318558 , G01R31/318572
摘要： A virtual In-Circuit Emulation (ICE) capability is provided herein for supporting testing of Joint Test Action Group (JTAG) hardware. A Virtual ICE Driver is configured for enabling any debug software to interface with target hardware in a flexible and scalable manner. The Virtual ICE Driver is configured such that the test instruction set used with the Virtual ICE Driver is not required to compute vectors, as the JTAG operations are expressed as local native instructions on scan segments, thereby enabling ICE resources to be accessed directly. The Virtual ICE Driver is configured such that ICE may be combined with instrument-based JTAG approaches (e.g., the IEEE P1687 standard and other suitable approaches). The Virtual ICE Driver is configured for receiving a plurality of scan segment operations generated by a plurality of target ICE controllers of at least one ICE host, scheduling the received scan segment operations, based at least in part on a scan chain of the target hardware, to form thereby a scheduled set of scan segment operations, and providing the scheduled set of scan segment operations to a processor configured for executing the scheduled set of scan segment operations for testing the target hardware.
摘要翻译：本文提供虚拟在线仿真（ICE）能力，用于支持联合测试动作组（JTAG）硬件的测试。虚拟ICE驱动程序被配置为使得任何调试软件能够以灵活和可扩展的方式与目标硬件进行接口。配置虚拟ICE驱动程序，使得与虚拟ICE驱动程序一起使用的测试指令集不需要计算向量，因为JTAG操作在扫描段上表示为本地本地指令，从而可以直接访问ICE资源。虚拟ICE驱动器被配置为使得ICE可以与基于仪器的JTAG方法（例如，IEEE P1687标准和其他合适的方法）组合。虚拟ICE驱动器被配置用于至少部分地基于目标硬件的扫描链接收由至少一个ICE主机的多个目标ICE控制器生成的多个扫描段操作，调度所接收的扫描段操作，从而形成预定的一组扫描段操作，以及将调度的扫描段操作集合提供给被配置为执行用于测试目标硬件的预定扫描段操作集合的处理器。

5. 发明授权

US08677198B2 Method and apparatus for system testing using multiple processors 有权
标题翻译：使用多个处理器进行系统测试的方法和装置
公开(公告)号：US08677198B2
公开(公告)日：2014-03-18
申请号：US12495295
申请日：2009-06-30
申请人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
发明人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
IPC分类号： G01R31/28
CPC分类号： G01R31/318558
摘要： An apparatus is provided for performing testing of at least a portion of a system under test via a Test Access Port (TAP) configured to access the system under test. The apparatus includes a first processor for executing instructions adapted for controlling testing of at least a portion of the system under test via the TAP, and a second processor for supporting an interface to the TAP. The first processor is configured for detecting, during execution of the test instructions, TAP-related instructions associated with control of the TAP, and propagating the TAP-related instructions toward the second processor. The second processor is configured for receiving the TAP-related instructions detected by the first processor and processing the TAP-related instructions. The first processor is configured for performing at least one task contemporaneously with processing of the TAP-related instructions by the second processor. An associated method also is provided.
摘要翻译：提供了一种用于经由被配置为访问被测系统的测试访问端口（TAP）来对待测系统的至少一部分进行测试的装置。该装置包括：第一处理器，用于执行适于经由TAP控制待测系统的至少一部分的测试的指令;以及第二处理器，用于支持与所述TAP的接口。第一处理器被配置为在执行测试指令期间检测与TAP的控制相关联的TAP相关指令，并将TAP相关指令传播到第二处理器。第二处理器被配置用于接收由第一处理器检测到的TAP相关指令并处理TAP相关指令。第一处理器被配置为与第二处理器处理与TAP相关的指令同时执行至少一个任务。还提供了相关联的方法。

6. 发明授权

US08621301B2 Method and apparatus for virtual in-circuit emulation 有权
标题翻译：用于虚拟在线仿真的方法和装置
公开(公告)号：US08621301B2
公开(公告)日：2013-12-31
申请号：US12827556
申请日：2010-06-30
申请人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
发明人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/3177 , G01R31/318558 , G01R31/318572
摘要： A virtual In-Circuit Emulation (ICE) capability is provided herein for supporting testing of Joint Test Action Group (JTAG) hardware. A Virtual ICE Driver is configured for enabling any debug software to interface with target hardware in a flexible and scalable manner. The Virtual ICE Driver is configured such that the test instruction set used with the Virtual ICE Driver is not required to compute vectors, as the JTAG operations are expressed as local native instructions on scan segments, thereby enabling ICE resources to be accessed directly. The Virtual ICE Driver is configured such that ICE may be combined with instrument-based JTAG approaches (e.g., the IEEE P1687 standard and other suitable approaches). The Virtual ICE Driver is configured for receiving a plurality of scan segment operations generated by a plurality of target ICE controllers of at least one ICE host, scheduling the received scan segment operations, based at least in part on a scan chain of the target hardware, to form thereby a scheduled set of scan segment operations, and providing the scheduled set of scan segment operations to a processor configured for executing the scheduled set of scan segment operations for testing the target hardware.
摘要翻译：本文提供虚拟在线仿真（ICE）能力，用于支持联合测试动作组（JTAG）硬件的测试。虚拟ICE驱动程序被配置为使得任何调试软件能够以灵活和可扩展的方式与目标硬件进行接口。配置虚拟ICE驱动程序，使得与虚拟ICE驱动程序一起使用的测试指令集不需要计算向量，因为JTAG操作在扫描段上表示为本地本地指令，从而可以直接访问ICE资源。虚拟ICE驱动器被配置为使得ICE可以与基于仪器的JTAG方法（例如，IEEE P1687标准和其他合适的方法）组合。虚拟ICE驱动器被配置为用于接收由至少一个ICE主机的多个目标ICE控制器产生的多个扫描段操作，至少部分地基于目标硬件的扫描链来调度所接收的扫描段操作，从而形成预定的一组扫描段操作，以及将调度的扫描段操作集合提供给被配置为执行用于测试目标硬件的预定扫描段操作集合的处理器。

7. 发明授权

US08533545B2 Method and apparatus for system testing using multiple instruction types 有权
标题翻译：使用多种指令类型进行系统测试的方法和装置
公开(公告)号：US08533545B2
公开(公告)日：2013-09-10
申请号：US12495237
申请日：2009-06-30
申请人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
发明人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
IPC分类号： G01R31/28
CPC分类号： G01R31/318558
摘要： An apparatus for use in testing at least a portion of a system under test via a Test Access Port (TAP) is provided. The apparatus includes a memory for storing a set of instructions of a test instruction set architecture and a processor executing the set of instructions of the test instruction set architecture for testing at least a portion of the system under test via the TAP. The set of instructions of the test instruction set architecture includes a first set of instructions including a plurality of instructions of an Instruction Set Architecture (ISA) supported by the processor and a second set of instructions including a plurality of test instructions associated with the TAP. The instructions of the first set of instructions and the instructions of the second set of instructions are integrated to form the set of instructions of the test instruction set architecture.
摘要翻译：提供了一种用于通过测试访问端口（TAP）测试被测系统的至少一部分的装置。该装置包括存储器，用于存储测试指令集体系结构的一组指令，以及执行测试指令集体系结构指令集的处理器，用于经由TAP测试待测系统的至少一部分。测试指令集架构的指令集包括第一组指令，其包括由处理器支持的指令集架构（ISA）的多个指令，以及包括与该TAP相关联的多个测试指令的第二组指令。第一组指令和第二组指令的指令的指令被集成以形成测试指令集架构的指令集。

8. 发明授权

US08495758B2 Method and apparatus for providing scan chain security 有权
标题翻译：提供扫描链安全性的方法和装置
公开(公告)号：US08495758B2
公开(公告)日：2013-07-23
申请号：US12818707
申请日：2010-06-18
申请人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
发明人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
IPC分类号： G06F1/26 , G06F11/00 , G08B13/00 , G08B21/00 , G08B29/00
CPC分类号： G01R31/31719 , G01R31/318572
摘要： A scan chain security capability is provided herein. The scan chain security capability enables secure control over normal use of a scan chain of a system, e.g., for purposes such as testing prior to deployment or sale of the system, in-field testing after deployment or sale of the system, in-field modification of the system, and the like. The scan chain security capability enables secure control over normal use of a scan chain by enabling control over interruption of a scan chain and re-establishment of an interrupted scan chain. A scan chain security component is configured for removing an open-circuit condition from the scan chain in response to a control signal. The control signal may be generated in response to validation of a security key, in response to successful completion of a challenge-based authentication process, or in response to any other suitable validation or authentication. The scan chain security component also may be configured for creating an open-circuit condition in the scan chain in response to a second control signal. The second control signal may be a scan register value received via the scan chain.
摘要翻译：本文提供扫描链安全功能。扫描链安全功能可以对系统的扫描链的正常使用进行安全控制，例如，用于系统部署或销售前的测试，部署或销售系统后的现场测试，现场系统的修改等。扫描链安全功能可以通过启用对扫描链的中断控制和重新建立中断的扫描链的安全控制扫描链的正常使用。扫描链安全组件被配置为响应于控制信号从扫描链中去除开路状况。响应于成功完成基于挑战的认证过程，或者响应于任何其他合适的验证或认证，可以响应于安全密钥的验证而产生控制信号。扫描链安全组件还可以被配置为响应于第二控制信号在扫描链中创建开路状况。第二控制信号可以是经由扫描链接收的扫描寄存器值。

9. 发明申请

US20100229042A1 METHOD AND APPARATUS FOR SYSTEM TESTING USING MULTIPLE PROCESSORS 有权
标题翻译：使用多个处理器进行系统测试的方法和装置
公开(公告)号：US20100229042A1
公开(公告)日：2010-09-09
申请号：US12495295
申请日：2009-06-30
申请人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
发明人： Suresh Goyal , Michele Portolan , Bradford Van Treuren
IPC分类号： G06F11/27 , G06F11/00
CPC分类号： G01R31/318558
摘要： An apparatus is provided for performing testing of at least a portion of a system under test via a Test Access Port (TAP) configured to access the system under test. The apparatus includes a first processor for executing instructions adapted for controlling testing of at least a portion of the system under test via the TAP, and a second processor for supporting an interface to the TAP. The first processor is configured for detecting, during execution of the test instructions, TAP-related instructions associated with control of the TAP, and propagating the TAP-related instructions toward the second processor. The second processor is configured for receiving the TAP-related instructions detected by the first processor and processing the TAP-related instructions. The first processor is configured for performing at least one task contemporaneously with processing of the TAP-related instructions by the second processor. An associated method also is provided.
摘要翻译：提供了一种用于经由被配置为访问被测系统的测试访问端口（TAP）来对待测系统的至少一部分进行测试的装置。该装置包括：第一处理器，用于执行适于经由TAP控制待测系统的至少一部分的测试的指令;以及第二处理器，用于支持与所述TAP的接口。第一处理器被配置为在执行测试指令期间检测与TAP的控制相关联的TAP相关指令，并将TAP相关指令传播到第二处理器。第二处理器被配置用于接收由第一处理器检测到的TAP相关指令并处理TAP相关指令。第一处理器被配置为与第二处理器处理与TAP相关的指令同时执行至少一个任务。还提供了相关联的方法。

10. 发明申请

US20070032999A1 System and method for emulating hardware failures and method of testing system software incorporating the same 审中-公开
标题翻译：用于仿真硬件故障的系统和方法以及包含该故障的系统软件的测试方法
公开(公告)号：US20070032999A1
公开(公告)日：2007-02-08
申请号：US11198119
申请日：2005-08-05
申请人： Eric Bauer , Bradford Van Treuren
发明人： Eric Bauer , Bradford Van Treuren
IPC分类号： G06F9/455
CPC分类号： G06F11/3664 , G06F11/3656
摘要： A system for, and method of, emulating hardware failures and a Joint Test Action Group (JTAG) test tool incorporating the same. In one embodiment, the system includes: (1) a vector generator configured to generate at least one device failure emulation vector and (2) a JTAG interface associable with the vector generator and configured to deliver the device failure emulation vector to hardware thereby to test system software associated with the hardware.
摘要翻译：用于仿真硬件故障的系统和方法以及包含该故障的联合测试动作组（JTAG）测试工具。在一个实施例中，该系统包括：（1）被配置为生成至少一个设备故障仿真向量的矢量发生器，和（2）与矢量发生器相关联并且被配置为将设备故障仿真向量传送到硬件的JTAG接口，与硬件相关的系统软件。

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