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1. 发明授权

US06599764B1 Isolation testing scheme for multi-die packages 失效
标题翻译：多芯片封装的隔离测试方案
公开(公告)号：US06599764B1
公开(公告)日：2003-07-29
申请号：US09870354
申请日：2001-05-30
申请人： Boon Jin Ang , Sammy Cheung , Kar Keng Chua
发明人： Boon Jin Ang , Sammy Cheung , Kar Keng Chua
IPC分类号： H01L2166
CPC分类号： G01R31/2886 , H01L2224/05554 , H01L2224/48091 , H01L2224/48145 , H01L2924/00014 , H01L2924/00012
摘要： A test platform is configured to test a mult-die package having at a first die and a second die. The test platform includes a first lead that is connected to the VCC input on the first die. The test platform also includes a second lead that is connected to VCCIO input on the second die. The VCC input on the second die is connected to ground. The I/O pin of the second die can then be tri-stated using a control circuit disposed between the pre-driver and the driver of the I/O buffer.
摘要翻译：测试平台被配置为测试具有在第一管芯和第二管芯处的多管芯封装。测试平台包括一个第一引线，连接到第一个管芯上的VCC输入端。测试平台还包括连接到第二个芯片上的VCCIO输入的第二引脚。第二个管芯上的VCC输入端接地。然后可以使用设置在I / O缓冲器的预驱动器和驱动器之间的控制电路来将第二管芯的I / O引脚三态化。

2. 发明授权

US08291355B2 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US08291355B2
公开(公告)日：2012-10-16
申请号：US12967851
申请日：2010-12-14
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： G06F17/50
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（HLE）的ASIC架构，提供FPGA等效FPGA以提供更高效和经济性，每个ASIC架构可以提供FPGA逻辑元件（LE）的全部功能的一部分）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

3. 发明授权

US08504963B2 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US08504963B2
公开(公告)日：2013-08-06
申请号：US13614819
申请日：2012-09-13
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： G06F17/50
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

4. 发明申请

US20130002295A1 APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS 有权
标题翻译：可编程逻辑及相关方法的应用特定集成电路等效
公开(公告)号：US20130002295A1
公开(公告)日：2013-01-03
申请号：US13614819
申请日：2012-09-13
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： H03K19/173
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（HLE）的ASIC架构，提供FPGA等效FPGA以提供更高效和经济性，每个ASIC架构可以提供FPGA逻辑元件（LE）的全部功能的一部分）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

5. 发明申请

US20110084727A1 APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS 有权
标题翻译：可编程逻辑及相关方法的应用特定集成电路等效
公开(公告)号：US20110084727A1
公开(公告)日：2011-04-14
申请号：US12967851
申请日：2010-12-14
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

6. 发明授权

US07243329B2 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
公开(公告)号：US07243329B2
公开(公告)日：2007-07-10
申请号：US10884460
申请日：2004-07-02
申请人： Kar Keng Chua , Sammy Cheung
发明人： Kar Keng Chua , Sammy Cheung
IPC分类号： G06F17/50 , G06F7/38 , H01L25/00
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

7. 发明授权

US07870513B2 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US07870513B2
公开(公告)日：2011-01-11
申请号：US11801082
申请日：2007-05-07
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： G06F17/50 , H03K19/173 , H03K19/177
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

8. 发明授权

US06489817B1 Clock divider using positive and negative edge triggered state machines 有权
标题翻译：时钟分频器使用正和负边缘触发状态机
公开(公告)号：US06489817B1
公开(公告)日：2002-12-03
申请号：US09965290
申请日：2001-09-26
申请人： Choong Kit Wong , Sammy Cheung , Boon Jin Ang
发明人： Choong Kit Wong , Sammy Cheung , Boon Jin Ang
IPC分类号： H03K2100
CPC分类号： H03K23/68
摘要： A clock divider is described. The clock divider includes: a positive edge triggered state machine having a first input for receiving a first input signal and a first output for providing a first output signal; a negative edge triggered state machine having a second input for receiving a second input signal and a second output for providing a second output signal; and a first combination logic coupled to the positive edge triggered state machine and the negative edge triggered state machine, the first combination logic having a third input for receiving third input signals and a third output for providing a third output signal, where (1) at least one of the first input signal and the second input signal includes an input clock signal having an input clock signal period, (2) the third input signals include the first output signal and the second output signal, and (3) the third output includes an output clock signal having an output clock signal period, where the output clock signal period is a multiple of the input clock signal period.
摘要翻译：描述了时钟分频器。时钟分频器包括：正沿触发状态机，具有用于接收第一输入信号的第一输入端和用于提供第一输出信号的第一输出端; 负边缘触发状态机，具有用于接收第二输入信号的第二输入和用于提供第二输出信号的第二输出; 以及耦合到所述正沿触发状态机和所述负沿触发状态机的第一组合逻辑，所述第一组合逻辑具有用于接收第三输入信号的第三输入和用于提供第三输出信号的第三输出，其中（1）第一输入信号和第二输入信号中的至少一个包括具有输入时钟信号周期的输入时钟信号，（2）第三输入信号包括第一输出信号和第二输出信号，以及（3）第三输出包括具有输出时钟信号周期的输出时钟信号，其中输出时钟信号周期是输入时钟信号周期的倍数。

9. 发明授权

US06281704B1 High-performance interconnect 有权
公开(公告)号：US06281704B1
公开(公告)日：2001-08-28
申请号：US09810116
申请日：2001-03-15
申请人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
发明人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
IPC分类号： H03K19177
摘要： Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

10. 发明申请

US20070210827A1 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US20070210827A1
公开(公告)日：2007-09-13
申请号：US11801082
申请日：2007-05-07
申请人： Kar Chua , Sammy Cheung , Hee Phoon , Kim Tan , Wei Goay
发明人： Kar Chua , Sammy Cheung , Hee Phoon , Kim Tan , Wei Goay
IPC分类号： H03K19/173
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

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