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1. 发明授权

US08796689B2 Thin film transistor array panel 有权
标题翻译：薄膜晶体管阵列面板
公开(公告)号：US08796689B2
公开(公告)日：2014-08-05
申请号：US13615210
申请日：2012-09-13
申请人： Bon-Yong Koo , Jeong Min Park , Ho Kyoon Kwon , Yun Hee Kwak
发明人： Bon-Yong Koo , Jeong Min Park , Ho Kyoon Kwon , Yun Hee Kwak
IPC分类号： H01L33/00
CPC分类号： H01L27/1214 , G02F1/13458 , G02F1/136227 , H01L27/124
摘要： A thin film transistor array panel includes a gate line and the driver connection line formed with the same layer material, a data line and a driving pad formed with the same layer material, a first field generating electrode and a connecting member formed with the same layer material, and a second field generating electrode and a dummy electrode layer formed with the same layer material.
摘要翻译：薄膜晶体管阵列面板包括栅极线和形成有相同层材料的驱动器连接线，形成有相同层材料的数据线和驱动焊盘，第一场产生电极和形成有相同层的连接构件材料和形成有相同层材料的第二场产生电极和虚拟电极层。

2. 发明申请

US20130069069A1 THIN FILM TRANSISTOR ARRAY PANEL 有权
标题翻译：薄膜晶体管阵列
公开(公告)号：US20130069069A1
公开(公告)日：2013-03-21
申请号：US13615210
申请日：2012-09-13
申请人： Bon-Yong Koo , Jeong Min Park , Ho Kyoon Kwon , Yun Hee Kwak
发明人： Bon-Yong Koo , Jeong Min Park , Ho Kyoon Kwon , Yun Hee Kwak
IPC分类号： H01L33/08
CPC分类号： H01L27/1214 , G02F1/13458 , G02F1/136227 , H01L27/124
摘要： A thin film transistor array panel includes a gate line and the driver connection line formed with the same layer material, a data line and a driving pad formed with the same layer material, a first field generating electrode and a connecting member formed with the same layer material, and a second field generating electrode and a dummy electrode layer formed with the same layer material.
摘要翻译：薄膜晶体管阵列面板包括栅极线和形成有相同层材料的驱动器连接线，形成有相同层材料的数据线和驱动焊盘，第一场产生电极和形成有相同层的连接构件材料和形成有相同层材料的第二场产生电极和虚拟电极层。

3. 发明授权

US09024858B2 Display panel with improved gate driver 有权
标题翻译：显示面板具有改进的栅极驱动器
公开(公告)号：US09024858B2
公开(公告)日：2015-05-05
申请号：US13442583
申请日：2012-04-09
申请人： Bon-Yong Koo , Beom Jun Kim , Ho Kyoon Kwon
发明人： Bon-Yong Koo , Beom Jun Kim , Ho Kyoon Kwon
IPC分类号： G09G3/36 , G11C19/28 , G11C19/00
CPC分类号： G09G3/36 , G09G2310/0267 , G09G2310/0286 , G09G2320/0209 , G11C19/28
摘要： The present invention divides a wire supplying a scan start signal to a gate driver into two wires, so as to avoid overlapping a clock signal line. In this way the clock signal is not delayed by interference, and a gate driving margin may continue uninterrupted, thereby uniformly outputting a gate-on voltage. In particular, if the clock signal line is connected to all stages in the gate driver and the clock signal line overlaps the scan start signal line, unsightly horizontal bands appear on the image and the parallel gate lines generate a very large parasitic capacitance. In contrast, the gate drivers in the present disclosure comprise clock signal lines which do not overlap the scan start signal lines. As benefits, interference resulting in horizontal banding is minimized and the power consumption may be reduced by about 10%.
摘要翻译：本发明将将扫描开始信号提供给栅极驱动器的线分成两条线，以避免与时钟信号线重叠。以这种方式，时钟信号不被干扰延迟，并且栅极驱动裕度可以不间断地继续，从而均匀地输出栅极导通电压。特别地，如果时钟信号线连接到栅极驱动器中的所有级并且时钟信号线与扫描起始信号线重叠，则在图像上出现不好看的水平频带，并行栅极线产生非常大的寄生电容。相反，本公开的栅极驱动器包括不与扫描起始信号线重叠的时钟信号线。作为益处，导致水平条带的干扰被最小化，并且功耗可以降低大约10％。

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