专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120064724A1 Methods of Forming a Pattern of Semiconductor Devices 审中-公开
标题翻译：形成半导体器件图案的方法
公开(公告)号：US20120064724A1
公开(公告)日：2012-03-15
申请号：US13222447
申请日：2011-08-31
申请人： Bo-hee Lee , Kyoung-mi Kim , Jeong-ju Park , Mi-ra Park , Jae-ho Kim , Young-ho Kim
发明人： Bo-hee Lee , Kyoung-mi Kim , Jeong-ju Park , Mi-ra Park , Jae-ho Kim , Young-ho Kim
IPC分类号： H01L21/308
CPC分类号： H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： Methods of forming a pattern of a semiconductor device including performing a double patterning process without using an atomic layer deposition (ALD) oxide film are provided. The methods may include forming a mask pattern on a substrate; forming a chemical attach process (CAP) material layer covering at least a portion of the mask pattern; forming a CAP adhesive layer by adhering at least a portion of the CAP material layer to the mask pattern by using a first baking process and a first development process; forming an interlayer covering at least a portion of the mask pattern and the CAP adhesive layer; and removing the mask pattern and the interlayer while allowing the CAP adhesive layer to remain by using a second baking process and a second development process.
摘要翻译：提供了形成半导体器件的图案的方法，包括不使用原子层沉积（ALD）氧化物膜来执行双重图案化工艺。所述方法可以包括在衬底上形成掩模图案; 形成覆盖所述掩模图案的至少一部分的化学附着工艺（CAP）材料层; 通过使用第一烘烤处理和第一显影处理将CAP材料层的至少一部分粘附到掩模图案上形成CAP粘合剂层; 形成覆盖所述掩模图案和所述CAP粘合剂层的至少一部分的中间层; 以及通过使用第二烘烤处理和第二显影处理使CAP粘合剂层保持不动，从而去除掩模图案和中间层。

2. 发明申请

US20120064463A1 Method of Forming Micropatterns 审中-公开
标题翻译：形成微图案的方法
公开(公告)号：US20120064463A1
公开(公告)日：2012-03-15
申请号：US13223592
申请日：2011-09-01
申请人： Jeong-ju Park , Kyoung-mi Kim , Joo-hyung Yang , Bo-hee Lee , Min-jung Kim , Jae-ho Kim , Young-ho Kim
发明人： Jeong-ju Park , Kyoung-mi Kim , Joo-hyung Yang , Bo-hee Lee , Min-jung Kim , Jae-ho Kim , Young-ho Kim
IPC分类号： G03F7/20
CPC分类号： G03F7/0392 , G03F7/325 , G03F7/40 , H01L21/0337
摘要： Provided is a method of forming micropatterns, in which a line-and-space pattern is formed using a positive photoresist, and a spin-on-oxide (SOX) spacer is formed on two sidewalls of the line-and-space pattern and used in etching a lower layer, thereby doubling a pattern density. Accordingly, all operations may be performed in single equipment (lithography equipment) without taking a substrate out, and thus a high throughput is obtained, and concerns about pollution are very low. Moreover, as the line-and-space pattern is formed using a wet method by using a negative tone developer, line-width roughness (LWR) of the micropatterns may be improved compared to when a dry etching method is used.
摘要翻译：提供一种形成微图案的方法，其中使用正性光致抗蚀剂形成线间距图案，并且在线间距图案的两个侧壁上形成自旋氧化物（SOX）间隔物，并使用在蚀刻下层，从而使图案密度加倍。因此，可以在单个设备（光刻设备）中执行所有操作，而不需要将衬底取出，从而获得高生产量，并且对污染的担忧非常低。此外，由于通过使用负色调显影剂使用湿法形成线间距图案，与使用干蚀刻方法相比，可以提高微图案的线宽粗糙度（LWR）。

3. 发明授权

US07615446B2 Charge trap flash memory device, fabrication method thereof, and write/read operation control method thereof 有权
标题翻译：电荷阱闪存器件及其制造方法及其读/写操作控制方法
公开(公告)号：US07615446B2
公开(公告)日：2009-11-10
申请号：US11580102
申请日：2006-10-13
申请人： Tae-whan Kim , Young-ho Kim , Jae-ho Kim , Jea-hun Jung , Chong-seung Yoon
发明人： Tae-whan Kim , Young-ho Kim , Jae-ho Kim , Jea-hun Jung , Chong-seung Yoon
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , B82Y10/00 , H01L29/7887
摘要： In one aspect, a charge trap flash memory device is provided which includes a semiconductor substrate, source and drain regions which are spaced apart in an active region of the semiconductor substrate to define a channel region therebetween, a tunneling dielectric layer located on the channel region, an organic polymer thin film located on the tunneling dielectric layer, metal or metal oxide nano-crystals embedded in the organic polymer thin film, and a gate located on the organic polymer thin film.
摘要翻译：一方面，提供了一种电荷阱闪存器件，其包括半导体衬底，在半导体衬底的有源区域中间隔开的源极和漏极区域，以在其间限定沟道区域，位于沟道区域上的隧道电介质层位于隧道电介质层上的有机聚合物薄膜，嵌入有机聚合物薄膜中的金属或金属氧化物纳米晶体，以及位于有机聚合物薄膜上的栅极。

4. 发明申请

US20090001346A1 Non-Volatile Polymer Bistability Memory Device 审中-公开
标题翻译：非易失性聚合物双稳态存储器件
公开(公告)号：US20090001346A1
公开(公告)日：2009-01-01
申请号：US11815331
申请日：2005-09-26
申请人： Tae-whan Kim , Young-ho Kim , Jae-ho Kim , Jae-hum Jung , Young-bae Yoon , Sung-keun Lim
发明人： Tae-whan Kim , Young-ho Kim , Jae-ho Kim , Jae-hum Jung , Young-bae Yoon , Sung-keun Lim
IPC分类号： H01L47/00 , H01L21/3205
CPC分类号： G11C13/0016 , B82Y10/00 , G11C13/0014 , H01L45/10 , H01L45/1233 , H01L45/14 , H01L45/1608
摘要： The present invention relates to non-volatile memory device utilizing multi-layered self-assembled Ni1-xFex nanocrystalline arrays embedded in a polymer thin film without source and drain regions and the fabrication method thereof. It is possible to fabricate nano-crystallines more simply than hitherto method according to the present invention. More particularly, it is possible to control size and density of nano-crystallines without agglomeration of the crystallines since the crystallines, which have uniform distribution, are besieged to polymer layer. Furthermore, the present invention provides the non-volatile bistable memory device having chemical and electrical stability of higher efficiency and lower cost than conventional flash memory devices with a nano floating gate. Also, source and drain region is unnecessary in the device of the present invention, it can reduce the throughput time and cost.
摘要翻译：本发明涉及利用嵌入无源极和漏极区域的聚合物薄膜中的多层自组装Ni1-xFex纳米晶阵列的非易失性存储器件及其制造方法。与根据本发明的方法相比，可以更简单地制造纳米结晶。更具体地，可以控制纳米结晶的尺寸和密度，而不会使结晶团聚，因为具有均匀分布的结晶被包围在聚合物层上。此外，本发明提供了具有比具有纳米浮动栅极的常规闪存器件更高效率和更低成本的化学和电气稳定性的非易失性双稳态存储器件。此外，在本发明的装置中，源极和漏极区域是不必要的，其可以减少生产时间和成本。

5. 发明申请

US20070102750A1 Charge trap flash memory device, fabrication method thereof, and write/read operation control method thereof 有权
标题翻译：电荷阱闪存器件及其制造方法及其读/写操作控制方法
公开(公告)号：US20070102750A1
公开(公告)日：2007-05-10
申请号：US11580102
申请日：2006-10-13
申请人： Tae-whan Kim , Young-ho Kim , Jae-ho Kim , Jea-hun Jung , Chong-seung Yoon
发明人： Tae-whan Kim , Young-ho Kim , Jae-ho Kim , Jea-hun Jung , Chong-seung Yoon
IPC分类号： H01L29/76
CPC分类号： H01L29/42332 , B82Y10/00 , H01L29/7887
摘要： In one aspect, a charge trap flash memory device is provided which includes a semiconductor substrate, source and drain regions which are spaced apart in an active region of the semiconductor substrate to define a channel region therebetween, a tunneling dielectric layer located on the channel region, an organic polymer thin film located on the tunneling dielectric layer, metal or metal oxide nano-crystals embedded in the organic polymer thin film, and a gate located on the organic polymer thin film.
摘要翻译：一方面，提供了一种电荷阱闪存器件，其包括半导体衬底，在半导体衬底的有源区域中间隔开的源极和漏极区域，以在其间限定沟道区域，位于沟道区域上的隧道电介质层位于隧道电介质层上的有机聚合物薄膜，嵌入有机聚合物薄膜中的金属或金属氧化物纳米晶体，以及位于有机聚合物薄膜上的栅极。

6. 发明申请

US20070064175A1 Nonvolatile polymer bistability memory device using nano particles that are formed in polymer thin film and method of manufacturing the nonvolatile polymer bistability memory device 审中-公开
标题翻译：使用在聚合物薄膜中形成的纳米颗粒的非挥发性聚合物双稳态记忆装置和制造非挥发性聚合物双稳态记忆装置的方法
公开(公告)号：US20070064175A1
公开(公告)日：2007-03-22
申请号：US11521394
申请日：2006-09-15
申请人： Tae-whan Kim , Young-ho Kim , Jae-ho Kim , Jea-hun Jung
发明人： Tae-whan Kim , Young-ho Kim , Jae-ho Kim , Jea-hun Jung
IPC分类号： G02F1/1333
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , G11C2213/77 , H01L27/2472 , H01L27/285 , H01L27/286 , H01L45/10 , H01L45/1233 , H01L45/14 , H01L45/1608 , H01L51/0035
摘要： A nonvolatile polymer bistability memory device using nano particles that are formed in a polymer thin film and a method of manufacturing the nonvolatile polymer bistability memory device are provided. The nonvolatile polymer bistability memory device includes a semiconductor substrate, a first electrode on the semiconductor substrate, a polymer thin film on the first electrode, nano particles embedded into the polymer thin film, and a second electrode on the polymer thin film. The nonvolatile polymer bistability memory device does not need any source and drain to operate, and the method of manufacturing the nonvolatile polymer bistability memory device can guarantee high production efficiencies while maintaining low manufacturing costs.
摘要翻译：提供了使用形成在聚合物薄膜中的纳米颗粒的非挥发性聚合物双稳态记忆装置和制造非挥发性聚合物双稳态记忆装置的方法。非挥发性聚合物双稳态记忆装置包括半导体衬底，半导体衬底上的第一电极，第一电极上的聚合物薄膜，嵌入聚合物薄膜中的纳米颗粒和聚合物薄膜上的第二电极。非挥发性聚合物双稳态记忆装置不需要任何源和漏来操作，并且制造非挥发性聚合物双稳态记忆装置的方法可以保持高的生产效率，同时保持低的制造成本。

7. 发明申请

US20090158385A1 Apparatus and method for automatically generating SELinux security policy based on selt 审中-公开
标题翻译：基于selt自动生成SELinux安全策略的设备和方法
公开(公告)号：US20090158385A1
公开(公告)日：2009-06-18
申请号：US12076783
申请日：2008-03-21
申请人： Dong-Wook Kim , Gyu-Il Cha , Young-ho Kim , Eun-Ji Lim , Soo-Young Kim , Sung-In Jung , Myung-Joon Kim , Bong-Nam Noh , Jung-Soon Kim
发明人： Dong-Wook Kim , Gyu-Il Cha , Young-ho Kim , Eun-Ji Lim , Soo-Young Kim , Sung-In Jung , Myung-Joon Kim , Bong-Nam Noh , Jung-Soon Kim
IPC分类号： G06F21/00
CPC分类号： G06F21/6218 , G06F21/604
摘要： Provided is an apparatus and method for automatically generating a SELinux security policy based on SELT. In the method, process generation is prepared by receiving execution file names of a program destined for policy generation. A system call log, which is traced by generating a process by executing the received execution file of the program, is stored. The traced system call log is purified into data necessary for generation of a security policy. Objects are grouped in consideration of the relationship between the objects based on purified information. A normalized data structure is recorded in an SELT description language format using a security policy file. Duplication and collision between the generated SELT security policy and the previous security policy in a system are detected.
摘要翻译：提供了一种基于SELT自动生成SELinux安全策略的装置和方法。在该方法中，通过接收用于策略生成的程序的执行文件名来准备进程生成。存储通过执行程序的接收到的执行文件生成处理来追踪的系统调用日志。跟踪的系统调用日志被净化为生成安全策略所需的数据。考虑到基于纯化信息的对象之间的关系对象进行分组。使用安全策略文件以SELT描述语言格式记录归一化数据结构。检测到生成的SELT安全策略与系统中之前的安全策略之间的重复和冲突。

8. 发明授权

US07448910B2 Displaying apparatus 失效
标题翻译：显示装置
公开(公告)号：US07448910B2
公开(公告)日：2008-11-11
申请号：US11216126
申请日：2005-09-01
申请人： Hyun-jin Chun , Young-ho Kim
发明人： Hyun-jin Chun , Young-ho Kim
IPC分类号： H01R33/76
CPC分类号： H01R13/7197 , H01R33/7635
摘要： A displaying apparatus includes a cathode ray tube (CRT), a printed circuit board (PCB) provided at a rear end of the CRT, a CRT socket to electrically connect the CRT and the PCB, a cable coupling part formed adjacent to the CRT socket, a high voltage cable coupled to the cable coupling part, and an electromagnetic wave shielding member provided inside the cable coupling part in contact with the high voltage cable to shield the displaying apparatus from electromagnetic waves generated by the high voltage cable. Thus the displaying apparatus is capable of shielding from electromagnetic waves generated in the process of applying high voltage to the CRT in a simple and effective manner.
摘要翻译：显示装置包括阴极射线管（CRT），设置在CRT后端的印刷电路板（PCB），CRT插座，用于电连接CRT和PCB;电缆耦合部件，其与CRT插座相邻形成耦合到所述电缆耦合部分的高压电缆以及设置在与所述高压电缆接触的所述电缆耦合部分内部的电磁波屏蔽部件，用于屏蔽所述显示装置免受由所述高压电缆产生的电磁波。因此，显示装置能够以简单有效的方式屏蔽在向CRT施加高电压的过程中产生的电磁波。

9. 发明申请

US20080223906A1 SOLDERING STRUCTURE AND METHOD USING ZN 有权
标题翻译：焊接结构和使用ZN的方法
公开(公告)号：US20080223906A1
公开(公告)日：2008-09-18
申请号：US11872066
申请日：2007-10-15
申请人： Won-kyoung Choi , Chang-youl Moon , Yoon-chul Son , Young-ho Kim , Hee-ra Roh , Chang-yul Oh
发明人： Won-kyoung Choi , Chang-youl Moon , Yoon-chul Son , Young-ho Kim , Hee-ra Roh , Chang-yul Oh
IPC分类号： B23K1/00 , B23K31/02 , B23K35/14
CPC分类号： B23K1/0016 , B23K35/262 , B23K35/282 , B23K2101/42 , H01L24/11 , H01L2224/05001 , H01L2224/0501 , H01L2224/05011 , H01L2224/05023 , H01L2224/05111 , H01L2224/05118 , H01L2224/05139 , H01L2224/05147 , H01L2224/05568 , H01L2224/05572 , H01L2224/05573 , H01L2224/05611 , H01L2224/05639 , H01L2224/05647 , H01L2224/1134 , H05K3/244 , H05K3/3463 , Y10T428/12493 , H01L2924/00014 , H01L2924/0103 , H01L2924/01029 , H01L2924/01028 , H01L2924/01047
摘要： A soldering structure using Zn includes a bonding layer which contains Zn; and a lead-free solder which bonds and reacts to the bonding layer. The bonding layer can be a Zn alloy layer or a multilayer including a Zn layer. Accordingly, the characteristics of the soldering structure can be improved by involving the high reactive Zn to the interfacial reaction of the soldering.
摘要翻译：使用Zn的焊接结构包括含有Zn的结合层; 以及与接合层结合并反应的无铅焊料。接合层可以是Zn合金层或包含Zn层的多层。因此，可以通过将高反应性Zn引入焊接的界面反应来提高焊接结构的特性。

10. 发明申请

US20070098355A1 Computer and monitor, display environment adjustment system and method comprising the same 有权
标题翻译：计算机和显示器，显示器环境调整系统及方法
公开(公告)号：US20070098355A1
公开(公告)日：2007-05-03
申请号：US11591594
申请日：2006-11-02
申请人： Young-ho Kim
发明人： Young-ho Kim
IPC分类号： H04N5/91 , H04N7/00
CPC分类号： G09G5/003 , G06F3/14 , G09G5/005 , G09G5/008 , G09G2320/08 , G09G2340/0464 , G09G2360/02 , G09G2370/042 , G09G2370/047
摘要： A display environment adjustment system and method are provided for a computer which comprises a connector with which a monitor is connected, and a video card supplying a video signal to the monitor through the connector, further comprising a program storage part which stores an auto adjustment program therein to control the video card supplying a pattern video signal according to a predetermined adjustment mode adjusting a display environment depending on the type of the monitor, and a controller which checks the type of the monitor when the monitor is connected with the connector, determines optimal adjustment environment information of the monitor by executing the auto adjustment program and supplies the pattern video signal according to the adjustment mode to the monitor based on the optimal adjustment environment information. Thus, the system and method provide a computer and monitor which display an optimal image by executing a display environment auto adjustment function through a video card connected with a monitor when the monitor is initially connected with the computer.
摘要翻译：提供一种用于计算机的显示环境调整系统和方法，所述计算机包括连接有监视器的连接器，以及通过连接器向监视器提供视频信号的视频卡，还包括存储自动调整程序的程序存储部件根据监视器的种类调整显示环境的预定调整模式，控制视频卡，以及当监视器与连接器连接时检查监视器的种类的控制器，确定最佳通过执行自动调整程序来监视监视器的调整环境信息，并且基于最佳调整环境信息将根据调整模式的图案视频信号提供给监视器。因此，当监视器最初与计算机连接时，系统和方法提供通过与监视器连接的视频卡执行显示环境自动调整功能来显示最佳图像的计算机和监视器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式