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1. 发明授权

US08927988B2 Self-sealed fluidic channels for a nanopore array 有权
标题翻译：用于纳米孔阵列的自密封流体通道
公开(公告)号：US08927988B2
公开(公告)日：2015-01-06
申请号：US13606904
申请日：2012-09-07
申请人： Bing Dang , Hongbo Peng
发明人： Bing Dang , Hongbo Peng
IPC分类号： H01L23/58 , B82Y15/00 , G01N33/487
CPC分类号： B82Y15/00 , G01N33/48721 , Y10S977/70 , Y10S977/704 , Y10S977/712 , Y10S977/84 , Y10S977/856
摘要： A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.
摘要翻译：形成纳米孔阵列的方法包括使衬底的前层图形化以形成前沟槽，所述衬底包括设置在前层和背层之间的掩埋层; 在图案化的前层和前沟槽上沉积膜层; 图案化背层和掩埋层以形成背沟，后沟与前沟槽对齐; 通过膜层形成多个纳米孔; 在前沟槽和后沟槽中沉积牺牲材料; 在所述牺牲材料上沉积前后绝缘层; 并且将所述牺牲材料加热至所述牺牲材料的分解温度以去除所述牺牲材料并形成一对前和后通道，其中每个通道对的前通道通过单独的纳米孔连接到其各自通道对的后通道。

2. 发明授权

US08518829B2 Self-sealed fluidic channels for nanopore array 有权
标题翻译：用于纳米孔阵列的自密封流体通道
公开(公告)号：US08518829B2
公开(公告)日：2013-08-27
申请号：US13092424
申请日：2011-04-22
申请人： Bing Dang , Hongbo Peng
发明人： Bing Dang , Hongbo Peng
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： B82Y15/00 , G01N33/48721 , Y10S977/70 , Y10S977/704 , Y10S977/712 , Y10S977/84 , Y10S977/856
摘要： A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.
摘要翻译：形成纳米孔阵列的方法包括使衬底的前层图形化以形成前沟槽，所述衬底包括设置在前层和背层之间的掩埋层; 在图案化的前层和前沟槽上沉积膜层; 图案化背层和掩埋层以形成背沟，后沟与前沟槽对齐; 通过膜层形成多个纳米孔; 在前沟槽和后沟槽中沉积牺牲材料; 在所述牺牲材料上沉积前后绝缘层; 并且将所述牺牲材料加热至所述牺牲材料的分解温度以去除所述牺牲材料并形成一对前和后通道，其中每个通道对的前通道通过单独的纳米孔连接到其相应通道对的后通道。

3. 发明申请

US20120326247A1 SELF-SEALED FLUIDIC CHANNELS FOR A NANOPORE ARRAY 有权
标题翻译：自封式流体通道用于NANOPORE ARRAY
公开(公告)号：US20120326247A1
公开(公告)日：2012-12-27
申请号：US13606904
申请日：2012-09-07
申请人： Bing Dang , Hongbo Peng
发明人： Bing Dang , Hongbo Peng
IPC分类号： H01L27/02 , B82Y5/00
CPC分类号： B82Y15/00 , G01N33/48721 , Y10S977/70 , Y10S977/704 , Y10S977/712 , Y10S977/84 , Y10S977/856
摘要： A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.
摘要翻译：形成纳米孔阵列的方法包括使衬底的前层图形化以形成前沟槽，所述衬底包括设置在前层和背层之间的掩埋层; 在图案化的前层和前沟槽上沉积膜层; 图案化背层和掩埋层以形成背沟，后沟与前沟槽对齐; 通过膜层形成多个纳米孔; 在前沟槽和后沟槽中沉积牺牲材料; 在所述牺牲材料上沉积前后绝缘层; 并且将所述牺牲材料加热至所述牺牲材料的分解温度以去除所述牺牲材料并形成一对前和后通道，其中每个通道对的前通道通过单独的纳米孔连接到其相应通道对的后通道。

4. 发明申请

US20120267729A1 SELF-SEALED FLUIDIC CHANNELS FOR NANOPORE ARRAY 有权
标题翻译：用于纳米阵列的自密封流体通道
公开(公告)号：US20120267729A1
公开(公告)日：2012-10-25
申请号：US13092424
申请日：2011-04-22
申请人： Bing Dang , Hongbo Peng
发明人： Bing Dang , Hongbo Peng
IPC分类号： H01L29/66 , H01L21/02
CPC分类号： B82Y15/00 , G01N33/48721 , Y10S977/70 , Y10S977/704 , Y10S977/712 , Y10S977/84 , Y10S977/856
摘要： A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.
摘要翻译：形成纳米孔阵列的方法包括使衬底的前层图形化以形成前沟槽，所述衬底包括设置在前层和背层之间的掩埋层; 在图案化的前层和前沟槽上沉积膜层; 图案化背层和掩埋层以形成背沟，后沟与前沟槽对齐; 通过膜层形成多个纳米孔; 在前沟槽和后沟槽中沉积牺牲材料; 在所述牺牲材料上沉积前后绝缘层; 并且将所述牺牲材料加热至所述牺牲材料的分解温度以去除所述牺牲材料并形成一对前和后通道，其中每个通道对的前通道通过单独的纳米孔连接到其相应通道对的后通道。

5. 发明授权

US08679280B2 Laser ablation of adhesive for integrated circuit fabrication 有权
标题翻译：用于集成电路制造的粘合剂的激光烧蚀
公开(公告)号：US08679280B2
公开(公告)日：2014-03-25
申请号：US12788839
申请日：2010-05-27
申请人： Bing Dang , Matthew Farinelli , John Knickerbocker , Aparna Prabhakar , Robert E. Trzcinski , Cornelia K. Tsang
发明人： Bing Dang , Matthew Farinelli , John Knickerbocker , Aparna Prabhakar , Robert E. Trzcinski , Cornelia K. Tsang
IPC分类号： B32B38/10
CPC分类号： H01L21/6835 , B23K26/0622 , B23K26/0823 , B23K26/361 , B23K26/57 , B23K2101/40 , B23K2103/42 , B23K2103/50 , C09J5/00 , C09J2203/326 , C09J2205/302 , C09J2400/22 , H01L2221/68381 , Y10T156/1158 , Y10T156/1917
摘要： A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC), includes attaching the handler to the wafer using an adhesive comprising a thermoset polymer, the handler comprising a material that is transparent in a wavelength range of about 193 nanometers (nm) to about 400 nm; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer.
摘要翻译：一种用于从晶片释放处理器的方法，所述晶片包括集成电路（IC），包括使用包含热固性聚合物的粘合剂将所述处理器附接到所述晶片，所述处理器包括在约193的波长范围内是透明的材料纳米（nm）至约400nm; 使用激光器通过处理器烧蚀粘合剂，其中基于处理材料的透明度选择激光的波长; 并将处理器与晶片分离。

6. 发明授权

US08419895B2 Laser ablation for integrated circuit fabrication 有权
标题翻译：激光烧蚀用于集成电路制造
公开(公告)号：US08419895B2
公开(公告)日：2013-04-16
申请号：US12788843
申请日：2010-05-27
申请人： Bing Dang , John Knickerbocker , Aparna Prabhakar , Peter Sorce , Robert E. Trzcinski , Cornelia K. Tsang
发明人： Bing Dang , John Knickerbocker , Aparna Prabhakar , Peter Sorce , Robert E. Trzcinski , Cornelia K. Tsang
IPC分类号： B32B38/10
CPC分类号： H01L21/6835 , B23K26/361 , H01L2221/68381 , Y10T156/1111 , Y10T156/1158 , Y10T156/1917
摘要： A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC) includes attaching the handler to the wafer using an adhesive comprising a polymer; performing edge processing to remove an excess portion of the adhesive from an edge of the handler and wafer; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. A system for releasing a handler from a wafer, the wafer comprising an IC includes a handler attached to a wafer using an adhesive comprising a polymer; an edge processing module, the edge processing module configured to remove an excess portion of the adhesive from the edge of the handler and wafer; and a laser, the laser configured to ablate the adhesive through the handler.
摘要翻译：一种用于从晶片释放处理器的方法，包括集成电路（IC）的晶片包括使用包含聚合物的粘合剂将处理器附接到晶片; 执行边缘处理以从处理器和晶片的边缘去除多余的粘合剂部分; 使用激光器通过处理器烧蚀粘合剂，其中基于处理材料的透明度选择激光的波长; 并将处理器与晶片分离。一种用于从晶片释放处理器的系统，包括IC的晶片包括使用包含聚合物的粘合剂附接到晶片的处理器; 边缘处理模块，所述边缘处理模块被配置为从所述处理器和晶片的边缘去除所述粘合剂的多余部分; 和激光器，激光器被配置为通过处理器消融粘合剂。

7. 发明申请

US20120326290A1 SILICON CARRIER OPTOELECTRONIC PACKAGING 有权
标题翻译：硅载体光电包装
公开(公告)号：US20120326290A1
公开(公告)日：2012-12-27
申请号：US13604341
申请日：2012-09-05
申请人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chrirag S. Patel
发明人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chrirag S. Patel
IPC分类号： H01L23/34 , H01L21/50
CPC分类号： H01L27/1446 , G02B6/4204 , G02B6/4249 , G02B6/4257 , G02B6/428 , G02B6/4292 , H01L23/367 , H01L25/16 , H01L27/14625 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01S5/005 , H01S5/0224 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H01S5/02407 , H01S5/02476 , H01S5/183 , H01S5/423 , H01L2924/014 , H01L2924/00
摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
摘要翻译：公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。硅层具有允许光通过的光通孔。光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。多个OE元件耦合到硅层并与布线电连通。至少一个OE元件被定位成与用于接收光的光通孔光学对准。载体介于电互连元件之间。载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

8. 发明申请

US20090311849A1 METHODS OF SEPARATING INTEGRATED CIRCUIT CHIPS FABRICATED ON A WAFER 审中-公开
标题翻译：在波形上分离集成电路芯片的方法
公开(公告)号：US20090311849A1
公开(公告)日：2009-12-17
申请号：US12140492
申请日：2008-06-17
申请人： Paul S. Andry , Bing Dang , Matthew J. Farinelli , Cornelia K. Tsang
发明人： Paul S. Andry , Bing Dang , Matthew J. Farinelli , Cornelia K. Tsang
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L21/6836 , H01L2221/68327 , H01L2221/68354 , H01L2221/68381 , H01L2224/16 , H01L2924/14
摘要： Improved methods of separating integrated circuit chips fabricated on a single wafer are provided. In an embodiment, a method of separating integrated circuit chips fabricated on a wafer comprises: attaching a support to a back surface of the wafer; dicing the wafer to form individual integrated circuit chips attached to the support; attaching a carrier comprising a releasable adhesive material to a front surface of the wafer opposite from the back surface; separating the support from the back surface of the wafer; subjecting the carrier to an effective amount of heat, radiation, or both to reduce the adhesiveness of the adhesive material to allow for removal of at least one of the integrated circuit chips from the carrier; and picking up and moving at least one of the integrated circuit chips using a tool configured to handle the integrated circuit chips.
摘要翻译：提供了分离在单个晶片上制造的集成电路芯片的改进的方法。在一个实施例中，分离在晶片上制造的集成电路芯片的方法包括：将支撑件附接到晶片的背面; 切割晶片以形成附接到支撑件的单个集成电路芯片; 将包含可释放粘合剂材料的载体附接到所述晶片的与所述后表面相对的前表面; 将支撑体从晶片的背面分离; 使载体经受有效量的热量，辐射或两者以降低粘合剂材料的粘附性，以允许将集成电路芯片中的至少一个从载体上移除; 以及使用构造成处理集成电路芯片的工具来拾取和移动至少一个集成电路芯片。

9. 发明申请

US20090178275A1 Silicon Carrier Including An Integrated Heater For Die Rework And Wafer Probe 审中-公开
标题翻译：包括用于芯棒返修和晶片探头的集成加热器的硅载体
公开(公告)号：US20090178275A1
公开(公告)日：2009-07-16
申请号：US12348115
申请日：2009-01-02
申请人： Bing Dang , Steven L. Wright
发明人： Bing Dang , Steven L. Wright
IPC分类号： H05K3/00
CPC分类号： H01L23/345 , H01L23/147 , H01L23/5384 , H01L24/81 , H01L24/98 , H01L25/0655 , H01L2224/16235 , H01L2224/81234 , H01L2224/81815 , H01L2924/01033 , H01L2924/01082 , H01L2924/09701 , H01L2924/14 , Y10T29/4913 , H01L2924/00
摘要： Forming a silicon carrier interposer having an integrated heater includes forming a multi-layer silicon member having a main body portion including a first surface, a second surface and an intermediate portion, and attaching first and second electronic components to the first surface of the multi-layer silicon member. A plurality of vias extend between the first surface and the second surface and are adapted to provide an interface between the first and second electronic components and a substrate. In addition, a plurality of heating elements are integrated into the main body portion of the multi-layer silicon member. The heating elements are selectively activated to create a reflow of solder to facilitate one of an attachment of one of the first and second electronic components to the multi-layer silicon member and a detachment of the one of the first and second electronic components from the multi-layer silicon member.
摘要翻译：形成具有集成加热器的硅载体插入件包括形成具有包括第一表面，第二表面和中间部分的主体部分的多层硅元件，以及将第一和第二电子元件附接到多层硅片的第一表面，层硅构件。多个通孔在第一表面和第二表面之间延伸并且适于提供第一和第二电子部件与基板之间的界面。另外，多层加热元件集成在多层硅构件的主体部分中。加热元件被选择性地激活以产生焊料的回流，以促进第一和第二电子元件中的一个附着到多层硅元件中的一个以及第一和第二电子元件中的一个与多层硅元件的分离层硅构件。

10. 发明授权

US09273408B2 Direct injection molded solder process for forming solder bumps on wafers 有权
标题翻译：用于在晶圆上形成焊料凸块的直接注塑成型焊接工艺
公开(公告)号：US09273408B2
公开(公告)日：2016-03-01
申请号：US13612812
申请日：2012-09-12
申请人： Bing Dang , Michael A. Gaynes , Paul A. Lauro , Jae-Woong Nah
发明人： Bing Dang , Michael A. Gaynes , Paul A. Lauro , Jae-Woong Nah
IPC分类号： B23K1/20 , C25D5/02 , H01L21/02 , H01L23/00 , C25D7/12 , H05K3/34
CPC分类号： H01L24/11 , C25D5/022 , C25D7/123 , H01L21/02107 , H01L24/13 , H01L24/16 , H01L24/742 , H01L24/81 , H01L2224/11001 , H01L2224/11002 , H01L2224/11312 , H01L2224/1141 , H01L2224/11462 , H01L2224/1147 , H01L2224/1162 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/81801 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H05K3/3436 , H05K2201/10734 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01026 , H01L2924/00
摘要： Solder bumps are provided on round wafers through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned mask layer. Solder is injected over the pillars or BLM, filling the channels. Molten solder can be injected in cavities formed in round wafers without leakage using a carrier assembly that accommodates wafers that have been previously subjected to mask layer deposition and patterning. One such carrier assembly includes an elastomeric body portion having a round recess, the walls of the recess forming a tight seal with the round wafer. Other carrier assemblies employ adhesives applied around the peripheral edges of the wafers to ensure sealing between the carrier assemblies and wafers.
摘要翻译：通过使用注射成型焊料在圆形晶片上提供焊料凸块。在图案化掩模层的通道内的I / O焊盘上形成铜柱或极限极限冶金。焊料注入柱子或BLM，填充通道。可以使用容纳预先经过掩模层沉积和图案化的晶片的载体组件将熔融的焊料注入到圆形晶片形成的空腔中而不发生泄漏。一个这样的载体组件包括具有圆形凹部的弹性体主体部分，凹部的壁与圆形晶片形成紧密密封。其他载体组件使用施加在晶片的周边边缘周围的粘合剂，以确保载体组件和晶片之间的密封。

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