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1. 发明申请

US20160364898A1 OPTIMIZING FOR RENDERING WITH CLEAR COLOR 有权
标题翻译：优化渲染与清晰的颜色
公开(公告)号：US20160364898A1
公开(公告)日：2016-12-15
申请号：US14737302
申请日：2015-06-11
申请人： Bimal Poddar , Prasoonkumar Surti , Rahul P. Sathe
发明人： Bimal Poddar , Prasoonkumar Surti , Rahul P. Sathe
IPC分类号： G06T15/00 , G06T19/20 , G06T15/50 , G06T1/60 , G06T15/04
CPC分类号： G06T15/005 , G06T1/60 , G06T15/04 , G06T15/506 , G06T19/20 , G06T2200/04 , G06T2200/28 , G06T2210/62
摘要： Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.
摘要翻译：实施例提供了一种包括渲染逻辑的图形处理装置，用于检测将导致具有与初始清除颜色值相同的数据的帧缓冲器的渲染操作，并将这种渲染操作变形为通常对初始清除帧缓冲器而进行的优化。

2. 发明授权

US09984490B2 Optimizing for rendering with clear color 有权
公开(公告)号：US09984490B2
公开(公告)日：2018-05-29
申请号：US14737302
申请日：2015-06-11
申请人： Bimal Poddar , Prasoonkumar Surti , Rahul P. Sathe
发明人： Bimal Poddar , Prasoonkumar Surti , Rahul P. Sathe
IPC分类号： G06T15/00 , G06T1/60 , G06T15/04 , G06T15/50 , G06T19/20
CPC分类号： G06T15/005 , G06T1/60 , G06T15/04 , G06T15/506 , G06T19/20 , G06T2200/04 , G06T2200/28 , G06T2210/62
摘要： Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

3. 发明申请

US20190261122A1 AUGMENTED REALITY VIRTUAL REALITY RAY TRACING SENSORY ENHANCEMENT SYSTEM, APPARATUS AND METHOD 审中-公开
公开(公告)号：US20190261122A1
公开(公告)日：2019-08-22
申请号：US16269778
申请日：2019-02-07
申请人： Joydeep Ray , Travis T. Schluessler , Prasoonkumar Surti , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , James M. Holland , Jeffery S. Boles , Jonathan Kennedy , Louis Feng , Atsuo Kuwahara , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Mayuresh M. Varerkar
发明人： Joydeep Ray , Travis T. Schluessler , Prasoonkumar Surti , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , James M. Holland , Jeffery S. Boles , Jonathan Kennedy , Louis Feng , Atsuo Kuwahara , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Mayuresh M. Varerkar
IPC分类号： H04S7/00 , G09B21/00 , H04R1/40 , G06T15/06 , G06F3/01 , G06T1/20 , H04R3/00
摘要： Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

5. 发明申请

US20140306970A1 Ordering Threads as Groups in a Multi-Threaded, Multi-Core Graphics Compute System 有权
标题翻译：在多线程，多核图形计算系统中将线程订购为组
公开(公告)号：US20140306970A1
公开(公告)日：2014-10-16
申请号：US13862542
申请日：2013-04-15
申请人： Prasoonkumar Surti , Thomas A. Piazza
发明人： Prasoonkumar Surti , Thomas A. Piazza
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/3838 , G06F9/3851
摘要： A scoreboard may keep track of thread dependencies. A set of threads with a common characteristic may be grouped so that if that characteristic is changed, the group of threads can be accessed to account for that change. Examples for such a characteristic include various types of scoreboard address changes. When the characteristic is changed the group of threads are used to identify threads affected by the characteristic change.
摘要翻译：记分牌可能会跟踪线程依赖关系。具有共同特征的一组线程可以被分组，使得如果该特性被改变，则可以访问该线程组以考虑该改变。这种特征的示例包括各种类型的记分板地址变化。当特性改变时，线程组用于识别受特征变化影响的线程。

6. 发明申请

US20140240328A1 TECHNIQUES FOR LOW ENERGY COMPUTATION IN GRAPHICS PROCESSING 审中-公开
标题翻译：图形处理中低能耗计算的技术
公开(公告)号：US20140240328A1
公开(公告)日：2014-08-28
申请号：US13777644
申请日：2013-02-26
申请人： Prasoonkumar Surti , Thomas A. Piazza
发明人： Prasoonkumar Surti , Thomas A. Piazza
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F1/3206 , G06F1/329 , Y02D10/24 , Y02D50/20
摘要： Techniques and architecture are disclosed for using a latency first-in/first-out (FIFO) to modally enable and disable a compute block in a graphics pipeline. In some example embodiments, the latency FIFO collects valid accesses for a downstream compute and integrates invalid inputs (e.g., bubbles), while the compute is in an off state (e.g., sleep). Once a sufficient number of valid accesses are stored in the latency FIFO, the compute is turned on, and the latency FIFO drains a burst of valid inputs thereto. In some embodiments, this burst helps to prevent or reduce any underutilization of the compute which otherwise might occur, thus providing power savings for a graphics pipeline or otherwise improving the energy efficiency of a given graphics system. In some instances, throughput demand at the latency FIFO input is maintained over a time window corresponding to the on and off time of the compute block.
摘要翻译：公开了使用延迟先进先出（FIFO）来模式地启用和禁用图形管线中的计算块的技术和架构。在一些示例性实施例中，等待时间FIFO在下游计算中收集有效访问，并且在计算处于关闭状态（例如睡眠）时对无效输入（例如，气泡）进行积分。一旦有足够数量的有效访问被存储在等待时间FIFO中，则计算被打开，并且等待时间FIFO向其中排出有效输入的脉冲串。在一些实施例中，该突发有助于防止或减少否则可能发生的计算的任何未充分利用，从而为图形管线提供功率节省或以其他方式提高给定图形系统的能量效率。在某些情况下，等待时间FIFO输入的吞吐量需求在对应于计算块的开启和关闭时间的时间窗口上被维持。

7. 发明授权

US07830397B2 Rendering multiple clear rectangles using a pre-rendered depth buffer 有权
标题翻译：使用预渲染深度缓冲区渲染多个清晰矩形
公开(公告)号：US07830397B2
公开(公告)日：2010-11-09
申请号：US12510610
申请日：2009-07-28
申请人： Prasoonkumar Surti , Hong Jiang , Steven J. Spangler
发明人： Prasoonkumar Surti , Hong Jiang , Steven J. Spangler
IPC分类号： G06T15/00 , G06T15/40 , G09G5/36 , G09G5/00 , G09G5/02 , G06K9/40 , G06K9/36
CPC分类号： G06T15/40 , H04N13/183 , H04N13/395
摘要： According to some embodiments, systems, methods, apparatus, computer program code and means are provided to set a first depth value associated with a plurality of pixels of a video image comprising a plurality of planes, create a first clear rectangle with respect to the first depth value, color render the pixels that are not associated with the first clear rectangle, and render the plurality of planes.
摘要翻译：根据一些实施例，提供系统，方法，装置，计算机程序代码和装置以设置与包括多个平面的视频图像的多个像素相关联的第一深度值，相对于第一深度值，颜色渲染与第一清除矩形不相关联的像素，并渲染多个平面。

8. 发明授权

US07760804B2 Efficient use of a render cache 有权
标题翻译：高效地使用渲染缓存
公开(公告)号：US07760804B2
公开(公告)日：2010-07-20
申请号：US10873684
申请日：2004-06-21
申请人： Brian E. Ruttenberg , Prasoonkumar Surti
发明人： Brian E. Ruttenberg , Prasoonkumar Surti
IPC分类号： H04N7/12 , G09G5/36
CPC分类号： G06T1/60 , G06F12/0875 , G06T15/005 , G09G5/363
摘要： Image data is processed into first and second component pixel blocks, where each of the first blocks is associated with a respective one of the second blocks to define a combination pixel block. The first and second blocks are written to memory through a cache that is used as a write buffer. The cache is logically partitioned into a contiguous portion to store the first blocks and not any second blocks, and another contiguous portion to store the second blocks and not any first blocks. Other embodiments are also described and claimed.
摘要翻译：图像数据被处理成第一和第二分量像素块，其中每个第一块与相应的第二块相关联以定义组合像素块。第一个和第二个块通过用作写入缓冲区的高速缓存写入存储器。高速缓存被逻辑地分割成连续部分以存储第一块而不是任何第二块，以及另外的连续部分来存储第二块而不是任何第一块。还描述和要求保护其他实施例。

9. 发明申请

US20050219253A1 Render-cache controller for multithreading, multi-core graphics processor 有权
标题翻译：用于多线程，多核图形处理器的渲染缓存控制器
公开(公告)号：US20050219253A1
公开(公告)日：2005-10-06
申请号：US10816052
申请日：2004-03-31
申请人： Thomas Piazza , Prasoonkumar Surti
发明人： Thomas Piazza , Prasoonkumar Surti
IPC分类号： G06F12/08 , G06T15/00 , G09G5/36 , G09G5/39
CPC分类号： G09G5/363 , G06F12/0804 , G06F12/0875 , G06T15/005
摘要： A method and apparatus for rendering three-dimensional graphics using a streaming render-cache with a multi-threading, multi-core graphics processor are disclosed. The graphics processor includes a streaming render-cache and render-cache controller to maintain the order in which threads are dispatched to the graphics engine, and to maintain data coherency between the render-cache and the main memory. The render-cache controller blocks threads from being dispatched to the graphics engine out of order by only allowing one sub-span to be in-flight at any given time.
摘要翻译：公开了一种使用具有多线程，多核图形处理器的流渲染缓存来呈现三维图形的方法和装置。图形处理器包括流渲染缓存和渲染缓存控制器，用于维护线程被分配到图形引擎的顺序，并且保持渲染缓存和主存储器之间的数据一致性。渲染缓存控制器通过仅允许一个子跨度在任何给定时间在飞行中来阻止线程被分派到图形引擎。

10. 发明申请

US20180308272A1 DEDICATED FIXED POINT BLENDING FOR ENERGY EFFICIENCY 审中-公开
公开(公告)号：US20180308272A1
公开(公告)日：2018-10-25
申请号：US15493195
申请日：2017-04-21
申请人： Abhishek R. Appu , Prasoonkumar Surti , Srivallaba Mysore , Subhajit Dasgupta , Hiroshi Akiba , Eric J. Hoekstra , Linda L. Hurd , Travis T. Schluessler , Daren J. Schmidt
发明人： Abhishek R. Appu , Prasoonkumar Surti , Srivallaba Mysore , Subhajit Dasgupta , Hiroshi Akiba , Eric J. Hoekstra , Linda L. Hurd , Travis T. Schluessler , Daren J. Schmidt
IPC分类号： G06T15/00 , G06F9/54 , G06F1/32 , G06T15/50
CPC分类号： G06T15/005 , G06T1/20 , G06T15/503
摘要： Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.

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