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1. 发明授权

US4274105A MOSFET Substrate sensitivity control 失效
标题翻译： MOSFET基板灵敏度控制
公开(公告)号：US4274105A
公开(公告)日：1981-06-16
申请号：US974594
申请日：1978-12-29
申请人： Billy L. Crowder , Fritz H. Gaensslen , Richard C. Jaeger
发明人： Billy L. Crowder , Fritz H. Gaensslen , Richard C. Jaeger
IPC分类号： H01L29/78 , H01L21/265 , H01L29/10 , H01L29/167
CPC分类号： H01L29/1033 , H01L21/26506 , H01L29/1054 , H01L29/167
摘要： The sensitivity of the threshold voltage in MOSFET devices to changes in substrate voltage may be reduced at a given temperature by the introduction of sufficiently deep energy level, low diffusivity impurities into the depletion region under the gate of the MOSFET.
摘要翻译： MOSFET器件中的阈值电压对于衬底电压变化的灵敏度可以通过在MOSFET的栅极下方的耗尽区域中引入足够深的能级，低扩散性杂质而在给定温度下降低。

2. 发明授权

US4128670A Fabrication method for integrated circuits with polysilicon lines having low sheet resistance 失效
标题翻译：具有薄板电阻低的多晶硅线路的集成电路的制造方法
公开(公告)号：US4128670A
公开(公告)日：1978-12-05
申请号：US850586
申请日：1977-11-11
申请人： Fritz H. Gaensslen
发明人： Fritz H. Gaensslen
IPC分类号： H01L29/78 , H01L21/28 , H01L21/321 , H01L21/336 , H01L21/768 , H01L23/532 , H01L29/423 , H01L29/43 , H01L29/49 , B05D5/12
CPC分类号： H01L29/66575 , H01L21/28052 , H01L21/321 , H01L21/76889 , H01L23/53271 , H01L29/4933 , H01L2924/0002 , Y10S148/147
摘要： A method and structure for polysilicon lines which include a silicide layer for providing a low sheet resistance. The invention may be employed in a polysilicon gate MOSFET process for integrated circuits as well as other integrated structures. In the method a first layer of polysilicon is deposited followed by a deposition of a metal of the silicide forming type. Another polysilicon layer is then deposited on top of the silicide forming metal to produce a three layer structure. The three layer structure is subjected to heat, for example, during the reoxidation step in a gate fabrication process, the metal reacts with the polysilicon at two reaction fronts to form a silicide. The resultant silicide has a much lower resistivity than doped polysilicon and therefore provides a second conductive layer which can be used more compatibly and efficiently in connection with the normal metal layer employed in integrated circuits to give a two-dimensional degree of freedom for the distribution of signals.
摘要翻译：一种用于多晶硅线路的方法和结构，其包括用于提供低薄层电阻的硅化物层。本发明可以用于集成电路的多晶硅栅极MOSFET工艺以及其它集成结构。在该方法中，沉积第一层多晶硅，然后沉积硅化物形成型金属。然后将另一多晶硅层沉积在硅化物形成金属的顶部上以产生三层结构。三层结构例如在栅极制造工艺中的再氧化步骤中受热，金属在两个反应面与多晶硅反应形成硅化物。所得到的硅化物具有比掺杂多晶硅低得多的电阻率，因此提供第二导电层，其可以与集成电路中使用的正常金属层相比较更加兼容和有效地使用，以提供二维自由度来分布信号。

3. 发明授权

US4268952A Method for fabricating self-aligned high resolution non planar devices employing low resolution registration 失效
标题翻译：用于制造采用低分辨率配准的自对准高分辨率非平面器件的方法
公开(公告)号：US4268952A
公开(公告)日：1981-05-26
申请号：US28461
申请日：1979-04-09
申请人： Fritz H. Gaensslen , Eberhard A. Spiller
发明人： Fritz H. Gaensslen , Eberhard A. Spiller
IPC分类号： H01L29/80 , H01L21/027 , H01L21/033 , H01L21/3205 , H01L21/338 , H01L29/78 , H01L29/812 , H01L21/302
CPC分类号： H01L29/812 , H01L21/0271 , H01L21/033
摘要： A method is disclosed for fabricating structures having electrically conductive regions such as high resolution semiconductor device and circuit designs which require only low resolution alignment steps during fabrication. The method is used to fabricate metal semiconductor field effect transistors (MESFET) and metal oxide semiconductor field effect transistors (MOSFET) devices and incorporates the following features. A device with very small (i.e. submicron) dimensions is positioned in a relatively large device well such that the exact position of the device in its well is not critical. Isolation and interconnection of devices in different wells is achieved by standard masking and alignment techniques with a resolution corresponding to the larger dimensions of the device wells. All high resolution features of the device are contained in a single masking level, however, to separate and insulate different elements of the device at such small dimensions different height levels are used in the device so that one masking step can produce zero lateral spacing between the different device elements. The disclosure provides examples of the present method applied to the fabrication of a MESFET device and a MOSFET device and to the isolation and interconnection of single devices into large circuits on a semiconductor chip.
摘要翻译：公开了用于制造具有导电区域的结构的方法，例如在制造期间仅需要低分辨率对准步骤的高分辨率半导体器件和电路设计。该方法用于制造金属半导体场效应晶体管（MESFET）和金属氧化物半导体场效应晶体管（MOSFET）器件，并结合以下特征。具有非常小（即亚微米）尺寸的装置位于相对较大的装置中，使得装置在其井中的确切位置不是关键的。通过标准掩蔽和对准技术实现不同井中的器件的隔离和互连，其分辨率对应于器件阱的较大尺寸。然而，器件的所有高分辨率特征都包含在单个掩蔽级中，然而，为了在这样小的尺寸上分离和绝缘器件的不同元件，在器件中使用不同的高度级别，使得一个掩模步骤可以产生零的横向间隔不同的设备元素。本公开提供了应用于制造MESFET器件和MOSFET器件的本方法以及将单个器件隔离和互连到半导体芯片上的大电路中的示例。

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