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1. 发明授权

US6025255A Two-step etching process for forming self-aligned contacts 失效
标题翻译：用于形成自对准触点的两步蚀刻工艺
公开(公告)号：US6025255A
公开(公告)日：2000-02-15
申请号：US105106
申请日：1998-06-25
申请人： Bi-Ling Chen , Erik S. Jerry , Daniel Hao-Tien Lee
发明人： Bi-Ling Chen , Erik S. Jerry , Daniel Hao-Tien Lee
IPC分类号： H01L21/311 , H01L21/60 , H01L21/306
CPC分类号： H01L21/76897 , H01L21/31116
摘要： The practice of forming self-aligned contacts in MOSFETs using a silicon nitride gate sidewall and a silicon nitride gate cap has found wide acceptance, particularly in the manufacture of DRAMs, where bitline contacts are formed between two adjacent wordlines, each having a nitride sidewall. The contact etch requires a an RIE etch having a high oxide/nitride selectivity. Current etchants rely upon the formation of a polymer over nitride surfaces which enhances oxide/nitride selectivity. However, for contact widths of less than 0.35 microns, as are encountered in high density DRAMs, the amount of polymer formation required to attain a high selectivity causes the contact opening to close over with polymer before the opening is completely etched. This results in opens or unacceptably resistive contacts. On the other hand, if the etchant is adjusted to produce too little polymer, the nitride cap and sidewalls are thinned or etched through, producing gate to source/drain shorts. The invention describes a two step etching process whereby the contact opening is initially etched at high selectivity, and then, as the contact channel narrows, the polymer formation rate is reduced to prevent polymer pinch off and assure clearance of insulator in the contact area. The method performs both etch steps and the polymer and photoresist removal successively within the same RIE tool.
摘要翻译：在使用氮化硅栅极侧壁和氮化硅栅极帽的MOSFET中形成自对准接触的做法已经被广泛接受，特别是在DRAM的制造中，其中在两个相邻字线之间形成位线接触，每个具有氮化物侧壁。接触蚀刻需要具有高氧化物/氮化物选择性的RIE蚀刻。目前的蚀刻剂依赖于在氮化物表面上形成聚合物，这增强了氧化物/氮化物的选择性。然而，如在高密度DRAM中遇到的小于0.35微米的接触宽度，获得高选择性所需的聚合物形成量使得在开口被完全蚀刻之前，接触开口与聚合物结合。这导致打开或不可接受的电阻触点。另一方面，如果蚀刻剂被调节以产生太少的聚合物，则氮化物盖和侧壁被薄化或蚀刻穿过，产生栅极到源极/漏极短路。本发明描述了一种两步蚀刻工艺，其中最初以高选择性蚀刻接触开口，然后随着接触通道变窄，降低聚合物形成速率以防止聚合物夹断并确保绝缘体在接触区域中的间隙。该方法在相同的RIE工具内连续执行蚀刻步骤和聚合物和光致抗蚀剂去除。

2. 发明授权

US5977558A Testchip design for process analysis in sub-micron DRAM fabrication 有权
标题翻译：用于亚微米DRAM制造过程分析的芯片设计
公开(公告)号：US5977558A
公开(公告)日：1999-11-02
申请号：US208916
申请日：1998-12-10
申请人： Daniel Hao-Tien Lee
发明人： Daniel Hao-Tien Lee
IPC分类号： H01L23/544 , H01L23/58
CPC分类号： H01L22/34 , H01L2924/0002
摘要： Integrated circuit chips having large regions of different device density and topography are susceptible to local processing variations which give rise to systematic failures affecting some circuit regions and not others. Over-simplified test structures cannot signal these failures during processing. Memory chips have large regions of storage cell arrays serviced by sizeable peripheral regions consisting of logic circuits. The device density and configuration in each of these regions on the chip are quite different. During processing steps these regions present differently to the process agents such as chemical etchants and plasmas producing in local variations of processing rates occur which result in systematic under processing in one region or over processing in another. Memory chips are particularly prone to such variations and also lend themselves well to the design of product specific test structures for flagging these aberrations. Several test structures are described which are formed from regions of the integrated circuit product itself. The structures are designed to monitor specific process steps where such local variations occur. The invention teaches the use of product specific test structures for process monitoring of sub-micron DRAM integrated circuits. The structures described are portions of the cell array outfitted with test probe pads and are capable of measuring opens and shorts in wordlines and bitlines. Another structure comprises a testable string of bitline contacts.
摘要翻译：具有不同器件密度和形貌的较大区域的集成电路芯片容易受到本地处理变化的影响，这些变化引起影响一些电路区域而不是其他电路区域的系统故障。过度简化的测试结构在处理过程中无法表明这些故障。存储器芯片具有由逻辑电路组成的相当大的外围区域所服务的存储单元阵列的大区域。芯片上每个这些区域的器件密度和配置是完全不同的。在处理步骤期间，这些区域与处理剂不同地呈现，例如在处理速率的局部变化中产生的化学蚀刻剂和等离子体，这导致在一个区域中系统地处理或在另一个区域中处理过程。存储芯片特别容易发生这种变化，并且也适用于用于标记这些像差的产品特定测试结构的设计。描述了由集成电路产品本身的区域形成的几个测试结构。这些结构被设计为监测发生这种局部变化的具体过程步骤。本发明教导了使用产品特定的测试结构来进行亚微米DRAM集成电路的过程监控。所描述的结构是配备有测试探针垫的单元阵列的部分，并且能够测量字线和位线中的开口和短路。另一种结构包括可测试的位线触点串。

3. 发明授权

US5985363A Method of providing uniform photoresist coatings for tight control of image dimensions 失效
标题翻译：提供均匀的光刻胶涂层以紧实控制图像尺寸的方法
公开(公告)号：US5985363A
公开(公告)日：1999-11-16
申请号：US814129
申请日：1997-03-10
申请人： Gwo-Yuh Shiau , Shinn-Jhy Lian , Daniel Hao-Tien Lee , Li-Ming Wang , Hsiang-Wei Tseng
发明人： Gwo-Yuh Shiau , Shinn-Jhy Lian , Daniel Hao-Tien Lee , Li-Ming Wang , Hsiang-Wei Tseng
IPC分类号： G03F7/16 , H01L21/312 , B05D3/12 , B05D3/02 , H01L21/31
CPC分类号： G03F7/162 , H01L21/312
摘要： A method for providing a uniform coating of photoresist over substrate for defining high density integrated device and circuit patterns. This is accomplished by applying the photoresist onto the substrate in multiple, separate dispensing steps and leveling spins to attain the designed thickness uniformly over substrate having high topographic surfaces, thereby preserve the integrity of the critical dimension for multi-level alignments used in the fabrication of integrated devices and circuits.
摘要翻译：一种用于在衬底上提供均匀的光致抗蚀剂涂层以定义高密度集成器件和电路图案的方法。这通过在多个单独的分配步骤和调平旋转中将光致抗蚀剂施加到基板上来实现，以在具有高地形表面的基板上均匀地获得设计的厚度，从而保持制造中使用的多级对准的临界尺寸的完整性集成器件和电路。

4. 发明授权

US6069077A UV resist curing as an indirect means to increase SiN corner selectivity on self-aligned contact etching process 失效
标题翻译： UV抗蚀剂固化作为间接手段来增加自对准接触蚀刻工艺中的SiN角选择性
公开(公告)号：US6069077A
公开(公告)日：2000-05-30
申请号：US888636
申请日：1997-07-07
申请人： Daniel Hao-Tien Lee , Jun-Cheng Ko
发明人： Daniel Hao-Tien Lee , Jun-Cheng Ko
IPC分类号： H01L21/027 , H01L21/311 , H01L21/60 , H01L21/44
CPC分类号： H01L21/76897 , H01L21/0273 , H01L21/31144
摘要： A method of forming a self-aligned contact in the fabrication of an integrated circuit is described. Semiconductor device structures are formed on a semiconductor substrate wherein their top and side surfaces are covered by a silicon nitride layer. A diagonal width of the silicon nitride layer on the side surfaces is a critical dimension. A layer of silicon oxide is deposited over the device structures and contacting the substrate adjacent to at least one of the semiconductor device structures where the self-aligned contact is to be formed. The substrate is covered with a layer of photoresist which is patterned to provide an opening over the planned self-aligned contact. Thereafter, the photoresist is exposed to ultraviolet light whereby the photoresist layer is cured. The silicon oxide is etched away at a high temperature to provide an opening to the silicon substrate using the patterned and cured photoresist and the silicon nitride layer on the side surfaces as a mask wherein the high temperature provides high selectivity of the silicon nitride layer to the silicon oxide layer and wherein the critical dimension is maintained at a thickness sufficient to prevent a short between the semiconductor device structure and a conducting layer to be deposited within the opening. A conducting layer is deposited within the opening to complete the formation of the self-aligned contact.
摘要翻译：描述了在集成电路的制造中形成自对准接触的方法。半导体器件结构形成在半导体衬底上，其顶表面和侧表面被氮化硅层覆盖。侧面上的氮化硅层的对角宽度是关键尺寸。在器件结构上沉积氧化硅层，并且与衬底相邻接近要形成自对准接触的至少一个半导体器件结构。衬底被一层光致抗蚀剂覆盖，该层被图案化以在计划的自对准接触上提供开口。此后，将光致抗蚀剂暴露于紫外线，由此使光致抗蚀剂层固化。氧化硅在高温下被蚀刻掉以提供使用图案化和固化的光致抗蚀剂和侧表面上的氮化硅层作为掩模的硅衬底的开口，其中高温提供氮化硅层的高选择性氧化硅层，其中临界尺寸保持在足以防止半导体器件结构和导电层之间的短路沉积在开口内的厚度。导电层沉积在开口内以完成自对准接触的形成。

5. 发明授权

US5872018A Testchip design for process analysis in sub-micron DRAM fabrication 失效
标题翻译：用于亚微米DRAM制造过程分析的芯片设计
公开(公告)号：US5872018A
公开(公告)日：1999-02-16
申请号：US851596
申请日：1997-05-05
申请人： Daniel Hao-Tien Lee
发明人： Daniel Hao-Tien Lee
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： H01L22/34 , H01L2924/0002
摘要： Integrated circuit chips having large regions of different device density and topography are susceptible to local processing variations which give rise to systematic failures affecting some circuit regions and not others. Over simplified test structures cannot signal these failures during processing. Memory chips have large regions of storage cell arrays serviced by sizeable peripheral regions consisting of logic circuits. The device density and configuration in each of these regions on the chip are quite different. During processing steps these regions present differently to the process agents such as chemical etchants and plasmas producing in local variations of processing rates occur which result in systematic under processing in one region or over processing in another. Memory chips are particularly prone to such variations and also lend themselves well to the design of product specific test structures for flagging these aberrations. Several test structures are described which are formed from regions of the integrated circuit product itself. The structures are designed to monitor specific process steps where such local variations occur. The invention teaches the use of product specific test structures for process monitoring of sub-micron DRAM integrated circuits. The structures described are portions of the cell array outfitted with test probe pads and are capable of measuring opens and shorts in wordlines and bitlines. Another structure comprises a testable string of bitline contacts.
摘要翻译：具有不同器件密度和形貌的较大区域的集成电路芯片容易受到本地处理变化的影响，这些变化引起影响一些电路区域而不是其他电路区域的系统故障。在简化的测试结构中，处理过程中无法表明这些故障。存储器芯片具有由逻辑电路组成的相当大的外围区域所服务的存储单元阵列的大区域。芯片上每个这些区域的器件密度和配置是完全不同的。在处理步骤期间，这些区域与处理剂不同地呈现，例如在处理速率的局部变化中产生的化学蚀刻剂和等离子体，这导致在一个区域中系统地处理或在另一个区域中处理过程。存储芯片特别容易发生这种变化，并且也适用于用于标记这些像差的产品特定测试结构的设计。描述了由集成电路产品本身的区域形成的几个测试结构。这些结构被设计为监测发生这种局部变化的具体过程步骤。本发明教导了使用产品特定的测试结构来进行亚微米DRAM集成电路的过程监控。所描述的结构是配备有测试探针垫的单元阵列的部分，并且能够测量字线和位线中的开口和短路。另一种结构包括可测试的位线触点串。

6. 发明授权

US5700731A Method for manufacturing crown-shaped storage capacitors on dynamic random access memory cells 失效
标题翻译：在动态随机存取存储单元上制造冠状储能电容器的方法
公开(公告)号：US5700731A
公开(公告)日：1997-12-23
申请号：US568722
申请日：1995-12-07
申请人： John C. H. Lin , Daniel Hao-Tien Lee , Meng-Jaw Cherng
发明人： John C. H. Lin , Daniel Hao-Tien Lee , Meng-Jaw Cherng
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/1085 , H01L27/10817 , H01L28/40
摘要： A method for manufacturing an array of dynamic random access memory (DRAM) cells having a single crown-shaped or a double crown-shaped stacked capacitors is accomplished. The method involves forming an array of device areas on a silicon substrate in which FETs for the DRAM cells are formed. After forming bit line contacts and bit line metallurgy contacting one of the two source/drain areas of each FET, a thick low melting temperature glass (BPSG) is deposited and planarized by annealing. Node capacitor contact openings are formed in the BPSG using a polysilicon sidewall method that reduces the contact size, and a thick polysilicon layer is deposited to contact the node source/drain areas of the FETs, and also provides a planar polysilicon surface. A specially designed edge phase-shift mask is then used with a positive photoresist to pattern the thick polysilicon layer and form crown-shaped bottom electrodes. The capacitors are then completed by depositing a interelectrode dielectric and forming a polysilicon top electrode. A second phase-shift mask design is used to form a double crown-shaped capacitor. These new capacitors are estimated to increase the capacitance over the more conventional thick capacitor by about 50 and 115%, respectively.
摘要翻译：实现了具有单冠形或双冠形叠层电容器的动态随机存取存储器（DRAM）单元阵列的制造方法。该方法包括在其上形成用于DRAM单元的FET的硅衬底上形成器件区域阵列。在形成位线触点和位线冶金接触每个FET的两个源/漏区之一之后，通过退火沉积厚平的低熔点玻璃（BPSG）并使其平坦化。使用减小接触尺寸的多晶硅侧壁法在BPSG中形成节点电容器接触开口，沉积厚的多晶硅层以接触FET的节点源极/漏极区域，并且还提供平面多晶硅表面。然后将专门设计的边缘相移掩模与正性光致抗蚀剂一起使用以形成厚的多晶硅层并形成冠状的底部电极。然后通过沉积电极间电介质并形成多晶硅顶电极来完成电容器。第二相移掩模设计用于形成双冠状电容器。估计这些新的电容器分别比常规厚电容器增加约50和115％的电容。

7. 发明授权

US5429979A Method of forming a dram cell having a ring-type stacked capacitor 失效
标题翻译：形成具有环型叠层电容器的电容器的方法
公开(公告)号：US5429979A
公开(公告)日：1995-07-04
申请号：US274415
申请日：1994-07-13
申请人： Daniel Hao-Tien Lee , Chao-Ming Koh , Yu-Hua Lee
发明人： Daniel Hao-Tien Lee , Chao-Ming Koh , Yu-Hua Lee
IPC分类号： H01L21/8242 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852
摘要： A new method for fabricating a storage capacitor, on a dynamic random access memory (DRAM) cell, having a ring-type sidewall was accomplished. The method involves opening the self-aligned node contact to the source/drain area of the field effect transistor and forming the bottom capacitor electrode. The same photoresist mask used to open the self-aligned node contact is later used to mask and partially etch the polysilicon bottom capacitor electrode to form the ring-type sidewall on the bottom electrode. The storage capacitor is then completed by forming a thin capacitor dielectric and depositing the top electrode. The method provides a simple process that increases the capacitance of the storage capacitor by about 40 percent while not adversely affecting the leakage current.
摘要翻译：完成了在具有环型侧壁的动态随机存取存储器（DRAM）单元上制造存储电容器的新方法。该方法包括将自对准节点接触打开到场效应晶体管的源极/漏极区域并形成底部电容器电极。用于打开自对准节点接触的相同的光致抗蚀剂掩模稍后用于掩蔽并部分蚀刻多晶硅底部电容器电极以在底部电极上形成环型侧壁。然后通过形成薄的电容器电介质并沉积顶部电极来完成存储电容器。该方法提供了将存储电容器的电容增加约40％的简单过程，同时不会对漏电流产生不利影响。

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