专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070035328A1 Configurable logic element with expander structures 有权
公开(公告)号：US20070035328A1
公开(公告)日：2007-02-15
申请号：US11585534
申请日：2006-10-24
申请人： Bernard New , Ralph Wittig , Sundararajarao Mohan
发明人： Bernard New , Ralph Wittig , Sundararajarao Mohan
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , H03K19/1731 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

2. 发明申请

US20050062498A1 Configurable logic element with expander structures 有权
标题翻译：具有扩展器结构的可配置逻辑元件
公开(公告)号：US20050062498A1
公开(公告)日：2005-03-24
申请号：US10990227
申请日：2004-11-16
申请人： Bernard New , Ralph Wittig , Sundararajarao Mohan
发明人： Bernard New , Ralph Wittig , Sundararajarao Mohan
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17748 , H03K19/1731 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.
摘要翻译：用于现场可编程门阵列（FPGA）的可配置逻辑元件（CLE）包括“扩展器”，即允许逻辑块之间的快速信号通信的连接器。扩展器允许多个逻辑块或其部分的可配置互连形成可以实现诸如PAL，查找表，多路复用器，三态缓冲器和存储器之类的大型用户电路的单个逻辑实体。一个实施例包括可配置逻辑块。在第一模式中，逻辑块提供具有N个共享输入和两个单独输出的两个N输入LUT。然后使用扩展器组合输出以产生（N + 1） - 输入功能。在第二模式中，逻辑块提供具有M个非共享输入的两个N输入LUT。可选的第三模式基于N个输入信号的值提供多个产品项输出信号。

3. 发明申请

US20060230092A1 Architectural floorplan for a digital signal processing circuit 有权
标题翻译：数字信号处理电路的建筑平面布置图
公开(公告)号：US20060230092A1
公开(公告)日：2006-10-12
申请号：US11433369
申请日：2006-05-12
申请人： Alvin Ching , Jennifer Wong , Bernard New , James Simkins , John Thendean , Anna Wong , Vasisht Vadi
发明人： Alvin Ching , Jennifer Wong , Bernard New , James Simkins , John Thendean , Anna Wong , Vasisht Vadi
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.
摘要翻译：数字信号处理（DSP）块的物理平面图，包括：具有多个可编程互连元件的互连柱; 具有多个第一列的第一DSP元件，与所述互连列相邻定位的所述多个第一列中的第一输出寄存器列; 以及第二DSP元件，具有多个第二列，所述多个第二列的第二输出寄存器列与所述互连列相邻。

4. 发明申请

US20060190516A1 Digital signal processing element having an arithmetic logic unit 有权
标题翻译：具有算术逻辑单元的数字信号处理单元
公开(公告)号：US20060190516A1
公开(公告)日：2006-08-24
申请号：US11408364
申请日：2006-04-21
申请人： James Simkins , Jennifer Wong , Bernard New , Alvin Ching , John Thendean , Anna Wong , Vasisht Vadi , David Schultz
发明人： James Simkins , Jennifer Wong , Bernard New , Alvin Ching , John Thendean , Anna Wong , Vasisht Vadi , David Schultz
IPC分类号： G06F7/38
CPC分类号： G06K9/00986 , G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , H03K19/1737
摘要： A digital signal processing circuit including: a multiplier circuit; a plurality of. multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode.
摘要翻译：一种数字信号处理电路，包括：乘法器电路; 多个。耦合到乘法器电路并由第一操作码控制的多路复用器; 以及耦合到多个多路复用器并由第二操作码控制的算术逻辑单元。

5. 发明申请

US20060230093A1 Digital signal processing circuit having a pattern detector circuit for convergent rounding 有权
标题翻译：具有用于收敛四舍五入的图案检测器电路的数字信号处理电路
公开(公告)号：US20060230093A1
公开(公告)日：2006-10-12
申请号：US11432847
申请日：2006-05-12
申请人： Bernard New , Jennifer Wong , James Simkins , Alvin Ching , John Thendean , Anna Wong , Vasisht Vadi
发明人： Bernard New , Jennifer Wong , James Simkins , Alvin Ching , John Thendean , Anna Wong , Vasisht Vadi
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.
摘要翻译：一种用于收敛舍入的集成电路（IC），包括：加法器电路，被配置为产生求和; 比较电路，被配置为将所述求和与输入模式进行逐位比较，使用掩码对所述比较进行逐位掩码，并将所述掩蔽比较结合以产生比较位; 以及舍入电路，用于至少部分地基于所述比较位对所述求和进行舍入。

6. 发明申请

US20060212499A1 Digital signal processing block having a wide multiplexer 有权
标题翻译：具有宽多路复用器的数字信号处理块
公开(公告)号：US20060212499A1
公开(公告)日：2006-09-21
申请号：US11433120
申请日：2006-05-12
申请人： Bernard New , Vasisht Vadi , Jennifer Wong , Alvin Ching , John Thendean , Anna Wong , James Simkins
发明人： Bernard New , Vasisht Vadi , Jennifer Wong , Alvin Ching , John Thendean , Anna Wong , James Simkins
IPC分类号： G06F15/00
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.
摘要翻译：一种数字信号处理块，具有：1）第一数字信号处理元件，包括：第一多路复用器的第一多路复用器，所述第一多路复用器在第一数据输入和第一零常数输入之间进行选择; 以及耦合到所述第一多个复用器的第一算术单元，所述第一算术逻辑单元被配置为用于相加; 以及2）第二数字信号处理元件，包括：第二多路复用器的第二多路复用器，所述第二多路复用器在第二数据输入和第二零常数输入之间进行选择; 以及耦合到所述第二多路复用器的第二运算单元和所述第一多路复用器的第三多路复用器，所述第二运算单元被配置为相加。

7. 发明申请

US20060288070A1 Digital signal processing circuit having a pattern circuit for determining termination conditions 有权
标题翻译：具有用于确定终止条件的模式电路的数字信号处理电路
公开(公告)号：US20060288070A1
公开(公告)日：2006-12-21
申请号：US11433332
申请日：2006-05-12
申请人： Vasisht Vadi , Jennifer Wong , Bernard New , Alvin Ching , John Thendean , Anna Wong , James Simkins
发明人： Vasisht Vadi , Jennifer Wong , Bernard New , Alvin Ching , John Thendean , Anna Wong , James Simkins
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.
摘要翻译：一种用于从集成电路中的算术逻辑单元（ALU）检测模式的方法。该方法包括以下步骤：产生来自ALU的输出; 将ALU输出与模式进行比特比较以产生第一输出; 反转图案并将ALU输出与反转图案进行比较以产生第二输出; 使用多个掩模的掩码对第一和第二输出进行逐位掩蔽以产生第三和第四输出位; 组合第三和第四输出比特以产生第一和第二输出比较比特; 以及将第一和第二输出比较位存储在存储器中。

8. 发明申请

US20060206557A1 Arithmetic logic unit circuit 有权
标题翻译：算术逻辑单元电路
公开(公告)号：US20060206557A1
公开(公告)日：2006-09-14
申请号：US11433333
申请日：2006-05-12
申请人： Anna Wing Wah Wong , Jennifer Wong , Bernard New , Alvin Ching , John Thendean , James Simkins , Vasisht Mantra Vadi , David Schultz
发明人： Anna Wing Wah Wong , Jennifer Wong , Bernard New , Alvin Ching , John Thendean , James Simkins , Vasisht Mantra Vadi , David Schultz
IPC分类号： G06F7/50
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.
摘要翻译：一种算术逻辑单元，包括耦合到第一加法器的第一多路复用器，由第一操作码寄存器控制的第一多路复用器; 第二多路复用器，从第一加法器接收输入并耦合到第二加法器; 以及用于控制第二多路复用器，第一加法器或第二加法器中的一个或多个的第二操作码寄存器。第一和第二操作码寄存器中的位的组合构成ALU以执行一个或多个算术运算或一个或多个逻辑运算或其任何组合。

9. 发明申请

US20050039155A1 FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same 有权
公开(公告)号：US20050039155A1
公开(公告)日：2005-02-17
申请号：US10941248
申请日：2004-09-15
申请人： Bernard New
发明人： Bernard New
IPC分类号： H03K19/177 , G06F17/50 , G06F9/45
CPC分类号： H03K19/17736 , H03K19/17784 , H03K19/17792
摘要： An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments, the transistors of the first and second subsets have different threshold voltages. Transistors in the first subset, being optimized for speed, have a lower threshold voltage than transistors in the second subset, which are optimized for low power consumption. The difference in threshold voltages can be accomplished by using different doping levels, wells biased to different voltage levels, or using other well-known means. In some embodiments, the first subset of the interconnect resources includes buffers coupled to a higher voltage level than the second subset. In some embodiments, the first subset includes buffers manufactured using larger transistors than those in the second subset.

10. 发明申请

US20050021749A1 Method and apparatus for communication within a programmable logic device using serial transceivers 有权
标题翻译：使用串行收发器的可编程逻辑器件内的通信方法和装置
公开(公告)号：US20050021749A1
公开(公告)日：2005-01-27
申请号：US10420418
申请日：2003-04-21
申请人： Adam Donlin , Bernard New
发明人： Adam Donlin , Bernard New
IPC分类号： H03K19/177 , G06F15/173
CPC分类号： H03K19/17736
摘要： Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module. The first module and the second module each include a transceiver coupled to a serial/parallel interface, with each transceiver configured with at least one signal conductor for serial communication between the first module and the second module. The first module and the second module are configured to communicate with one another asynchronously. Each transceiver is configured to communicate with its respective serial/parallel interface in a synchronous time domain.
摘要翻译：描述了使用串行收发器的可编程逻辑器件内的通信方法和装置。在一个示例中，集成电路包括第一模块和第二模块。第一模块和第二模块各自包括耦合到串行/并行接口的收发器，每个收发器配置有用于第一模块和第二模块之间的串行通信的至少一个信号导体。第一模块和第二模块被配置为异步地彼此通信。每个收发器被配置为在同步时域中与其各自的串行/并行接口进行通信。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式