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1. 发明申请

US20090222683A1 Synchronization of Processor Time Stamp Counters to Master Counter 有权
标题翻译：处理器时间戳计数器与主计数器同步
公开(公告)号：US20090222683A1
公开(公告)日：2009-09-03
申请号：US12039140
申请日：2008-02-28
申请人： Benjamin C. Serebrin , Robert M. Kallal
发明人： Benjamin C. Serebrin , Robert M. Kallal
IPC分类号： G06F1/00
CPC分类号： G06F1/14
摘要： In one embodiment, an apparatus comprises one or more processors and a controller coupled to the processors. Each processor comprises at least one processor time stamp counter (TSC) and a first control unit configured to maintain the processor TSC. The controller comprises at least one controller TSC and a second control unit configured to maintain the controller TSC. The controller is configured to signal the processor responsive to determining that the processor TSC is out of synchronization with the controller TSC. In response to having been signalled that the processor TSC is out of synchronization, the processor is configured to resynchronize the processor TSC to the controller TSC before generating a result for a read TSC instruction. In response to having not been signalled that the processor TSC is out of synchronization, the processor is configured to generate the result responsive to the processor TSC without resynchronizing.
摘要翻译：在一个实施例中，一种装置包括一个或多个处理器和耦合到处理器的控制器。每个处理器包括至少一个处理器时间戳计数器（TSC）和被配置为维持处理器TSC的第一控制单元。控制器包括至少一个控制器TSC和被配置为维持控制器TSC的第二控制单元。控制器被配置为响应于确定处理器TSC与控制器TSC不同步而发信号通知处理器。响应于已经发信号通知处理器TSC不同步，处理器被配置为在为读取TSC指令生成结果之前将处理器TSC重新同步到控制器TSC。响应于没有发信号通知处理器TSC不同步，处理器被配置为响应于处理器TSC生成结果而不重新同步。

2. 发明授权

US07941684B2 Synchronization of processor time stamp counters to master counter 有权
标题翻译：处理器时间戳计数器与主计数器同步
公开(公告)号：US07941684B2
公开(公告)日：2011-05-10
申请号：US12039140
申请日：2008-02-28
申请人： Benjamin C. Serebrin , Robert M. Kallal
发明人： Benjamin C. Serebrin , Robert M. Kallal
IPC分类号： G06F1/12
CPC分类号： G06F1/14
摘要： In one embodiment, an apparatus comprises one or more processors and a controller coupled to the processors. Each processor comprises at least one processor time stamp counter (TSC) and a first control unit configured to maintain the processor TSC. The controller comprises at least one controller TSC and a second control unit configured to maintain the controller TSC. The controller is configured to signal the processor responsive to determining that the processor TSC is out of synchronization with the controller TSC. In response to having been signalled that the processor TSC is out of synchronization, the processor is configured to resynchronize the processor TSC to the controller TSC before generating a result for a read TSC instruction. In response to having not been signalled that the processor TSC is out of synchronization, the processor is configured to generate the result responsive to the processor TSC without resynchronizing.
摘要翻译：在一个实施例中，一种装置包括一个或多个处理器和耦合到处理器的控制器。每个处理器包括至少一个处理器时间戳计数器（TSC）和被配置为维持处理器TSC的第一控制单元。控制器包括至少一个控制器TSC和被配置为维持控制器TSC的第二控制单元。控制器被配置为响应于确定处理器TSC与控制器TSC不同步而发信号通知处理器。响应于已经发信号通知处理器TSC不同步，处理器被配置为在为读取TSC指令生成结果之前将处理器TSC重新同步到控制器TSC。响应于没有发信号通知处理器TSC不同步，处理器被配置为响应于处理器TSC生成结果而不重新同步。

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