专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4784965A Source drain doping technique 失效
标题翻译：源极漏极掺杂技术
公开(公告)号：US4784965A
公开(公告)日：1988-11-15
申请号：US097532
申请日：1987-09-16
申请人： Been-Jon Woo , Mark A. Holler , Ender Hokeler , Sandra S. Lee
发明人： Been-Jon Woo , Mark A. Holler , Ender Hokeler , Sandra S. Lee
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66598 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7836 , Y10S148/053 , Y10S148/082 , Y10S148/106
摘要： A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.
摘要翻译：描述了形成金属氧化物半导体场效应晶体管（MOSFET）的方法，其中源极和漏极区域以基本上垂直于衬底表面的方式通过离子注入以两个步骤设置，使得杂质的浓度随着横向距离而增加远离栅极电极部件抑制热注入，防止沟道效应，增加穿通电压并增加栅极辅助击穿电压。

2. 发明授权

US4728617A Method of fabricating a MOSFET with graded source and drain regions 失效
标题翻译：制造具有分级源极和漏极区域的MOSFET的方法
公开(公告)号：US4728617A
公开(公告)日：1988-03-01
申请号：US926733
申请日：1986-11-04
申请人： Been-Jon Woo , Mark A. Holler , Ender Hokelek , Sandra S. Lee
发明人： Been-Jon Woo , Mark A. Holler , Ender Hokelek , Sandra S. Lee
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66598 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7836 , Y10S148/053 , Y10S148/082 , Y10S148/106 , Y10S438/965
摘要： A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.
摘要翻译：描述了形成金属氧化物半导体场效应晶体管（MOSFET）的方法，其中源极和漏极区域以基本上垂直于衬底表面的方式通过离子注入以两个步骤设置，使得杂质的浓度随着横向距离而增加远离栅极电极部件抑制热注入，防止沟道效应，增加穿通电压并增加栅极辅助击穿电压。

3. 发明授权

US4757026A Source drain doping technique 失效
标题翻译：源极漏极掺杂技术
公开(公告)号：US4757026A
公开(公告)日：1988-07-12
申请号：US97539
申请日：1987-09-16
申请人： Been-Jon Woo , Mark A. Holler , Ender Hokelek , Sandra S. Lee
发明人： Been-Jon Woo , Mark A. Holler , Ender Hokelek , Sandra S. Lee
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66598 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7836 , Y10S148/082 , Y10S148/106
摘要： A method of forming complementary metal oxide semiconductor field-effect transistors (CMOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effects, to increase punch through voltage and to increase gate-aided breakdown voltage.
摘要翻译：描述了形成互补金属氧化物半导体场效应晶体管（CMOSFET）的方法，其中源极和漏极区域以基本上垂直于衬底表面的方式通过离子注入以两个步骤设置，使得杂质的浓度随着侧向距离栅电极部件的距离，以抑制热注入，防止通道效应，增加穿通电压并增加栅极辅助击穿电压。

4. 发明授权

US5075245A Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps 失效
标题翻译：用于改善掩埋位线闪速EPROM器件的擦除特性的方法，而不使用牺牲氧化物生长和去除步骤
公开(公告)号：US5075245A
公开(公告)日：1991-12-24
申请号：US642521
申请日：1991-01-17
申请人： Been-Jon Woo , Mark A. Holler
发明人： Been-Jon Woo , Mark A. Holler
IPC分类号： H01L21/32 , H01L21/336 , H01L21/8247
CPC分类号： H01L27/11521 , H01L21/32 , H01L29/66825 , Y10S148/114
摘要： A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. Ammonia formed during the field oxidation process reacts with the silicon substrate to form a thin silicon nitride layer in the beak region. A thin tunnel oxide is then grown without the use of a sacrificial-oxide growth and removal method. During tunnel oxide formation lateral growth of the field oxide is inhibited by the thin nitride layer previously formed. However, the tunnel oxide thinning (due to the existence of the thin nitride layer) induced low breakdown voltage is overcome by the enhanced oxide growth in the beak due to the buried source/drain dopants. The tunnel oxide in the erase regon is therefore uniform and thin. The thin, uniform oxide in the tunnel region leads to improved erase characteristics.
摘要翻译：用于制造闪存EPROM类型的非接触式电可编程和电可擦除存储器单元的方法。电池使用设置在场氧化物区域下方的细长的源极和漏极区域。在场氧化过程中形成的氨与硅衬底反应，以在喙部区域形成薄的氮化硅层。然后在不使用牺牲氧化物生长和去除方法的情况下生长薄的隧道氧化物。在隧道氧化物形成期间，场氧化物的横向生长被预先形成的薄氮化物层抑制。然而，隧道氧化物变薄（由于存在薄氮化物层）诱导的低击穿电压被由于埋入的源极/漏极掺杂剂引起的喙中增强的氧化物生长所克服。因此，擦除离子中的隧道氧化物是均匀和薄的。隧道区域中的薄均匀氧化物导致改善的擦除特性。

5. 发明授权

US5077230A Method for improving erase characteristics of buried bit line flash EPROM devices by use of a thin nitride layer formed during field oxide growth 失效
标题翻译：通过使用在场氧化物生长期间形成的薄氮化物层来改善掩埋位线闪速EPROM器件的擦除特性的方法
公开(公告)号：US5077230A
公开(公告)日：1991-12-31
申请号：US563098
申请日：1990-08-03
申请人： Been-Jon Woo , Mark A. Holler
发明人： Been-Jon Woo , Mark A. Holler
IPC分类号： H01L21/32 , H01L21/336 , H01L21/8247
CPC分类号： H01L27/11521 , H01L21/32 , H01L29/66825 , Y10S148/114
摘要： A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. Ammonia formed during the field oxidation process reacts with the silicon substrate to form a thin silicon nitride layer in the beak region. A thin tunnel oxide is then grown. During tunnel oxide formation lateral growth of the field oxide is inhibited by the thin nitride layer previously formed. However, the tunnel oxide thinning (due to the existence of the thin nitride layer) induced low breakdown voltage is overcome by the enhanced oxide growth in the beak due to the buried source/drain dopants. The tunnel oxide in the erase region is therefore uniform and thin. The thin, uniform oxide in the tunnel region leads to improved erase characteristics.
摘要翻译：用于制造闪存EPROM类型的非接触式电可编程和电可擦除存储器单元的方法。电池使用设置在场氧化物区域下方的细长的源极和漏极区域。在场氧化过程中形成的氨与硅衬底反应，以在喙部区域形成薄的氮化硅层。然后生长薄的隧道氧化物。在隧道氧化物形成期间，场氧化物的横向生长被预先形成的薄氮化物层抑制。然而，隧道氧化物变薄（由于存在薄氮化物层）诱导的低击穿电压被由于埋入的源极/漏极掺杂剂引起的喙中增强的氧化物生长所克服。因此，擦除区域中的隧道氧化物是均匀和薄的。隧道区域中的薄均匀氧化物导致改善的擦除特性。

6. 发明授权

US5146602A Method of increasing the accuracy of an analog neural network and the like 失效
标题翻译：提高模拟神经网络精度的方法等
公开(公告)号：US5146602A
公开(公告)日：1992-09-08
申请号：US634033
申请日：1990-12-26
申请人： Mark A. Holler , Simon M. Tam
发明人： Mark A. Holler , Simon M. Tam
IPC分类号： G06F15/18 , G06G7/60 , G06N3/063 , G06N99/00 , G11C27/00 , H01L29/788
CPC分类号： H01L29/7887 , G06N3/0635 , G11C27/005
摘要： A method for increasing the accuracy of an analog neural network which computers a sum-of-products between an input vector and a stored weight pattern is described. In one embodiment of the present invention, the method comprises initially training the network by programming the synapses with a certain weight pattern. The training may be carried out using any standard learning algorithm. Preferably, a back-propagation learning algorithm is employed.Next, network is baked at an elevated temperature to effectuate a change in the weight pattern previously programmed during initial training. This change results from a charge redistribution which occurs within each of the synapses of the network. After baking, the network is then retrained to compensate for the change resulting from the charge redistribution. The baking and retraining steps may be successively repeated to increase the accuracy of the neural network to any desired level.
摘要翻译：描述了一种用于增加计算输入向量和存储的权重模式之和的乘积的模拟神经网络的精度的方法。在本发明的一个实施例中，该方法包括通过以某种权重模式编程突触来初始训练网络。可以使用任何标准学习算法进行训练。优选地，采用反向传播学习算法。接下来，在升高的温度下烘烤网络，以实现在初始训练期间先前编程的重量模式的变化。这种变化是由于网络每个突触中发生的电荷再分配产生的。烘烤后，网络再次进行补充，以补偿由电荷重新分配引起的变化。烘焙和再培训步骤可以连续重复，以将神经网络的精度提高到任何所需的水平。

7. 发明授权

US4950917A Semiconductor cell for neural network employing a four-quadrant multiplier 失效
标题翻译：使用四象限乘法器的神经网络半导体单元
公开(公告)号：US4950917A
公开(公告)日：1990-08-21
申请号：US283553
申请日：1988-12-09
申请人： Mark A. Holler , Simon M. Tam , Ronald G. Benson , Hernan A. Castro
发明人： Mark A. Holler , Simon M. Tam , Ronald G. Benson , Hernan A. Castro
IPC分类号： G06G7/60 , G06F15/18 , G06N3/06 , G06N3/063 , G06N99/00 , H01L21/82 , H01L21/8238 , H01L21/8247 , H01L27/00 , H01L27/092 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G06N3/0635
摘要： A synapse cell for use in providing a weighted connection strength is disclosed. The cell employs a four-quadrant multiplier and a pair of floating gate devices. Various charge levels are programmed onto the floating gate devices, establishing weight and reference levels. These levels affect the current flowing through the multiplier. The output of the cell thus becomes a multiple of the input and the programmed charge difference.
摘要翻译：公开了一种用于提供加权连接强度的突触细胞。该单元采用四象限乘法器和一对浮栅器件。各种电荷电平被编程到浮动栅极器件上，建立重量和参考电平。这些水平影响流经乘数的电流。因此，单元的输出变为输入和编程的电荷差的倍数。

8. 发明授权

US4780424A Process for fabricating electrically alterable floating gate memory devices 失效
标题翻译：用于制造电可变浮动栅极存储器件的工艺
公开(公告)号：US4780424A
公开(公告)日：1988-10-25
申请号：US101642
申请日：1987-09-28
申请人： Mark A. Holler , Simon M. Tam
发明人： Mark A. Holler , Simon M. Tam
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/425 , H01L29/78
CPC分类号： H01L27/11521 , H01L27/115
摘要： A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The contactless cells use elongated source and drain regions disposed beneath field oxide regions. The drain regions are shallow compared to the source regions. The source regions have more graded junctions. Floating gates are formed over a tunnel oxide (120 .ANG. thick) between the source and drain regions with word lines being disposed perpendicular to the source and drain regions. One dimension of the floating gates is formed after the word lines have been patterned by etching the first layer of polysilicon in alignment with the word lines.
摘要翻译：用于制造闪存EPROM类型的非接触式电可编程和电可擦除存储器单元的方法。非接触式电池使用设置在场氧化物区域之下的细长的源极和漏极区域。漏极区域与源极区域相比较浅。源区具有更多的分级结。浮动栅极形成在源极和漏极区域之间的隧道氧化物（120安格姆厚）上，其字线垂直于源极和漏极区域设置。在通过蚀刻与字线对准的第一层多晶硅之后，在字线被图案化之后形成浮置栅极的一个维度。

9. 发明授权

US4460981A Virtual ground memory 失效
标题翻译：虚拟地面记忆
公开(公告)号：US4460981A
公开(公告)日：1984-07-17
申请号：US334304
申请日：1981-12-24
申请人： Michael A. Van Buskirk , Mark A. Holler
发明人： Michael A. Van Buskirk , Mark A. Holler
IPC分类号： G11C17/00 , G11C7/12 , G11C16/04 , G11C16/08 , G11C16/24 , G11C16/26 , G11C17/12 , G11C17/18 , G11C11/40
CPC分类号： G11C7/12 , G11C16/0491 , G11C16/08 , G11C16/24 , G11C16/26
摘要： A virtual ground memory array where alternate bit lines in the array are selectively coupled to ground. The other bit lines are coupled to an input/output line. Diode-like shunting is used between the bit lines to eliminate parasitic paths particularly for higher programming potentials such as used in EPROMs. Substantially no increase in overhead is required to control these diode-like paths since the architecture allows them to be controlled by address signals.
摘要翻译：虚拟接地存储器阵列，其中阵列中的交替位线选择性地耦合到地。其它位线耦合到输入/输出线。在位线之间使用二极管状分流以消除寄生路径，特别是用于较高编程电位，例如在EPROM中使用的。由于架构允许它们由地址信号控制，所以基本上不需要增加开销以控制这些二极管状路径。

10. 发明授权

US5028810A Four quadrant synapse cell employing single column summing line 失效
标题翻译：使用单列求和线的四象限突触细胞
公开(公告)号：US5028810A
公开(公告)日：1991-07-02
申请号：US526070
申请日：1990-05-18
申请人： Hernan A. Castro , Mark A. Holler
发明人： Hernan A. Castro , Mark A. Holler
IPC分类号： G06N3/063 , G11C15/04
CPC分类号： G11C15/046 , G06N3/063 , G06N3/0635
摘要： The present invention covers a synapse cell for providing a weighted connection between a differential input voltage and a single output summing line having an associated capacitance. The connection is made using one or more floating-gate transistors which provide both excitatory as well as inhibitory connections. As configured, each transistor's drain is coupled to an input line and its source is coupled to the output summing line. The floating-gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a voltage pulse having a certain duration is applied to the control gate of the floating-gate transistor, a current is generated which acts to discharge the capacitance associated with the output summing line. The current is directly proportional to the charge stored on the floating-gate member and the duration of the input pulse.
摘要翻译：本发明涵盖用于在差分输入电压和具有相关电容的单输出求和线之间提供加权连接的突触电池。使用一个或多个提供兴奋性和抑制性连接的浮栅晶体管进行连接。如所配置的，每个晶体管的漏极耦合到输入线，并且其源极耦合到输出求和线。晶体管的浮置栅极用于存储对应于神经连接的强度或重量的电荷。当具有一定持续时间的电压脉冲被施加到浮栅晶体管的控制栅极时，产生用于放电与输出求和线相关的电容的电流。电流与存储在浮栅器件上的电荷和输入脉冲的持续时间成正比。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式