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1. 发明授权

US06545869B2 Adjusting fillet geometry to couple a heat spreader to a chip carrier 有权
标题翻译：调整圆角几何以将散热器连接到芯片载体
公开(公告)号：US06545869B2
公开(公告)日：2003-04-08
申请号：US09764048
申请日：2001-01-17
申请人： Barry A. Bonitz , Eric Duchesne , Michael A. Gaynes , Eric A. Johnson
发明人： Barry A. Bonitz , Eric Duchesne , Michael A. Gaynes , Eric A. Johnson
IPC分类号： H05K720
CPC分类号： H01L23/4334 , H01L21/4882 , H01L21/563 , H01L23/3735 , H01L24/32 , H01L2224/73203 , H01L2224/83951 , H01L2924/01006 , H01L2924/01033 , H01L2924/351 , Y10T29/4913 , H01L2924/3512 , H01L2924/00
摘要： An electronic structure, and associated method of fabrication, for coupling a heat spreader above a chip to a chip carrier below the chip. Initially provided is a substrate, a chip on a surface of the substrate and coupled to the substrate, and the heat spreader. Then a fillet of at least one adhesive material is formed on the chip and around a periphery of the chip. Additionally, the heat spreader is placed on a portion of the fillet and over a top surface of the chip. The fillet couples the heat spreader to the substrate. An outer surface of the fillet makes a to contact angle of about 25 degrees with the surface of the substrate. The small contact angle not exceeding about 25 degrees prevents cracking of the substrate that would otherwise result from thermal cycling.
摘要翻译：一种用于将芯片上方的散热器与芯片下方的芯片载体耦合的电子结构及其制造方法。最初提供的是衬底，衬底的表面上的芯片并且耦合到衬底和散热器。然后在芯片上和芯片的周围形成至少一种粘合剂材料的圆角。此外，散热器放置在圆角的一部分上并且在芯片的顶表面上。圆角将散热器耦合到基板。圆角的外表面与衬底的表面形成约25度的接触角。小的接触角不超过约25度可以防止由于热循环而导致的基体的破裂。

2. 发明授权

US06984286B2 Adjusting fillet geometry to couple a heat spreader to a chip carrier 失效
公开(公告)号：US06984286B2
公开(公告)日：2006-01-10
申请号：US10338963
申请日：2003-01-08
申请人： Barry A. Bonitz , Eric Duchesne , Michael A. Gaynes , Eric A. Johnson
发明人： Barry A. Bonitz , Eric Duchesne , Michael A. Gaynes , Eric A. Johnson
IPC分类号： B32B31/20
CPC分类号： H01L23/4334 , H01L21/4882 , H01L21/563 , H01L23/3735 , H01L24/32 , H01L2224/73203 , H01L2224/83951 , H01L2924/01006 , H01L2924/01033 , H01L2924/351 , Y10T29/4913 , H01L2924/3512 , H01L2924/00
摘要： An electronic structure, and associated method of fabrication, for coupling a heat spreader above a chip to a chip carrier below the chip. Initially provided is a substrate, a chip on a surface of the substrate and coupled to the substrate, and the heat spreader. Then a fillet of at least one adhesive material is formed on the chip and around a periphery of the chip. Additionally, the heat spreader is placed on a portion of the fillet and over a top surface of the chip. The fillet couples the heat spreader to the substrate. An outer surface of the fillet makes a contact angle of about 25 degrees with the surface of the substrate. The small contact angle not exceeding about 25 degrees prevents cracking of the substrate that would otherwise result from thermal cycling.

3. 发明授权

US06410988B1 Thermally enhanced and mechanically balanced flip chip package and method of forming 失效
标题翻译：热增强和机械平衡倒装芯片封装和成型方法
公开(公告)号：US06410988B1
公开(公告)日：2002-06-25
申请号：US09570895
申请日：2000-05-15
申请人： David V. Caletka , Jean Dery , Eric Duchesne , Michael A. Gaynes , Eric A. Johnson , Luis J. Matienzo , James R. Wilcox
发明人： David V. Caletka , Jean Dery , Eric Duchesne , Michael A. Gaynes , Eric A. Johnson , Luis J. Matienzo , James R. Wilcox
IPC分类号： H01L2348
CPC分类号： H01L23/4334 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/10253 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2924/3512
摘要： A method of making a flip chip package that maintains flatness over a wide temperature range and provides good heat dissipation is described. A laminate substrate is electrically connected to electrical contacts disposed on a chip and underfill material is applied between the soldered connections. A body, for example an uncured dielectric material, is applied to the chip, the laminate substrate, a thermally conductive member or combinations thereof, and thermally conductive member is disposed adjacent to the surface of the chip that is opposite the surface connected to the laminate substrate. The body is extruded between the chip and the thermally conductive member. The thickness of the thermally conductive member is determined by balancing the stiffness and the CTE of both the thermally conductive member and the laminate substrate, and the length and width of the thermally conductive member may vary but are at least the size of the corresponding length and width of the chip.
摘要翻译：描述了制造在宽温度范围内保持平坦度并提供良好散热的倒装芯片封装的方法。层压基板电连接到设置在芯片上的电触头，底部填充材料被施加在焊接连接之间。例如未固化介电材料的主体被施加到芯片，层压基板，导热构件或其组合，并且导热构件设置在与连接到层压板的表面相对的芯片的表面附近基质。主体在芯片和导热构件之间挤出。导热构件的厚度通过平衡导热构件和层压衬底的刚度和CTE来确定，并且导热构件的长度和宽度可以变化，但是至少为相应长度的尺寸，并且芯片的宽度。

4. 发明授权

US6104093A Thermally enhanced and mechanically balanced flip chip package and method of forming 失效
公开(公告)号：US6104093A
公开(公告)日：2000-08-15
申请号：US80117
申请日：1998-05-15
申请人： David V. Caletka , Jean Dery , Eric Duchesne , Michael A. Gaynes , Eric A. Johnson , Luis J. Matienzo , James R. Wilcox
发明人： David V. Caletka , Jean Dery , Eric Duchesne , Michael A. Gaynes , Eric A. Johnson , Luis J. Matienzo , James R. Wilcox
IPC分类号： H01L23/31 , H01L23/433 , H01L23/48
CPC分类号： H01L23/4334 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/10253 , H01L2924/15311
摘要： A method of making a flip chip package that maintains flatness over a wide temperature range and provides good heat dissipation is described. A laminate substrate is electrically connected to electrical contacts disposed on a chip and underfill material is applied between the soldered connections. A body, for example an uncured dielectric material, is applied to the chip, the laminate substrate, a thermally conductive member or combinations thereof, and thermally conductive member is disposed adjacent to the surface of the chip that is opposite the surface connected to the laminate substrate. The body is extruded between the chip and the thermally conductive member. The thickness of the thermally conductive member is determined by balancing the stiffness and the CTE of both the thermally conductive member and the laminate substrate, and the length and width of the thermally conductive member may vary but are at least the size of the corresponding length and width of the chip.

5. 发明授权

US07176563B2 Electronically grounded heat spreader 失效
标题翻译：电子接地散热器
公开(公告)号：US07176563B2
公开(公告)日：2007-02-13
申请号：US10665997
申请日：2003-09-18
申请人： Eric Duchesne , Michael A. Gaynes
发明人： Eric Duchesne , Michael A. Gaynes
IPC分类号： H01L23/34
CPC分类号： H01L23/3737 , H01L24/32 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/07802 , H01L2924/14 , H01L2924/351 , H01L2924/00
摘要： Electronically grounded heat spreaders are employed in connection with the dissipation of heat, which is generated by electronic devices, such as semiconductor chips. Also provided is a novel method for the adhesive fastening of metallic heat spreaders to semiconductor chips through the combined use of electrically conductive and non-conductive adhesive materials.
摘要翻译：电子接地的散热器与由诸如半导体芯片的电子设备产生的热耗散结合使用。还提供了一种用于通过组合使用导电和非导电粘合剂材料将金属散热器粘合到半导体芯片上的新颖方法。

6. 发明申请

US20110166302A1 Method for Transforming a Single Reactor Line 有权
标题翻译：单电抗器线路转换方法
公开(公告)号：US20110166302A1
公开(公告)日：2011-07-07
申请号：US12280620
申请日：2007-02-21
申请人： Louis Fouarge , Eric Duchesne
发明人： Louis Fouarge , Eric Duchesne
IPC分类号： C08F2/01 , B01J8/00 , B23P17/00
CPC分类号： C08F2/01 , B01J8/007 , B01J19/1818 , B01J19/1837 , B01J2208/00176 , B01J2208/00619 , B01J2219/00024 , B01J2219/00031 , B01J2219/00033 , B01J2219/0004 , B01J2219/00094 , B01J2219/00184 , B01J2219/00254 , C08F10/02 , C08F110/02 , C08F210/16 , Y10T29/49716 , C08F2/14 , C08F210/14 , C08F2/001
摘要： The present invention discloses a method for transforming a single reactor line into a double reactor line wherein the existing single reactor line is equipped with a flash tank for separating the solid polymer product from the flash vapour and wherein the vapour is sent to a system of at least two separating columns allowing the separation of its constituents into monomer, diluent and comonomer.
摘要翻译：本发明公开了一种用于将单个反应器管线转化为双重反应器管线的方法，其中现有的单个反应器管线装备有用于将固体聚合物产物与闪蒸蒸气分离的闪蒸罐，并且其中蒸气被送至系统最少两个分离柱允许其组分分离成单体，稀释剂和共聚单体。

7. 发明授权

US07771541B2 Method of removing metallic, inorganic and organic contaminants from chip passivation layer surfaces 有权
标题翻译：从芯片钝化层表面去除金属，无机和有机污染物的方法
公开(公告)号：US07771541B2
公开(公告)日：2010-08-10
申请号：US11689570
申请日：2007-03-22
申请人： Claude Blais , Eric Duchesne , Kang-Wook Lee , Sylvain Ouimet , Gerald J. Scilla
发明人： Claude Blais , Eric Duchesne , Kang-Wook Lee , Sylvain Ouimet , Gerald J. Scilla
IPC分类号： B08B7/00 , C23F1/00
CPC分类号： H01L21/02057 , H01L23/3128 , H01L2224/16225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.
摘要翻译：去除和/或减少不需要的污染物的方法从芯片钝化层表面去除残留物，包括石墨层，氟化物层，硫酸钙（CaSO 4）颗粒，氧化锡和有机锡。该方法使用具有优化的等离子体参数的具有氩和氧混合物的等离子体处理以除去石墨和氟化层，并且从集成电路晶片中降低无机/锡氧化物/有机锡残余物的水平，同时保持重新沉积金属化合物可忽略不计。本发明公开了等离子体方法，有机物不会从聚合物重新沉积到焊球表面，氧化锡厚度在焊球上不增加。氩/氧的比例为约50％至约99％Ar和约1％至约50％体积的O 2。接下来的处理后的晶片被切割成用于制造倒装芯片塑料球栅阵列封装的单个芯片。

8. 发明申请

US20100175790A1 New Flux Composition and Process For Use Thereof 有权
标题翻译：新型助焊剂组合物及其使用方法
公开(公告)号：US20100175790A1
公开(公告)日：2010-07-15
申请号：US12731369
申请日：2010-03-25
申请人： Eric Duchesne , Kang-Wook Lee , Valerie Oberson
发明人： Eric Duchesne , Kang-Wook Lee , Valerie Oberson
IPC分类号： B23K35/34 , B23K35/36
CPC分类号： B23K35/362 , Y10T428/12493
摘要： The invention relates to a composition of matter comprising a soldering flux, wherein the flux consists essentially of a combination of a fluxing agent and a solvent, and wherein the fluxing agent comprises a keto acid such as levulinic acid or acetylbutyric acid. The flux may also comprises an ester acid, or comprises a mixture of the keto acid with the ester acid. The solvent comprises a mixture of a tacky solvent with a non-tacky solvent. The invention also relates to a process comprising soldering at least two surfaces together, each of which comprises a metal area to which solder can adhere by employing the following steps in any order: applying solder to at least one of the metal areas, aligning the metal areas so that they are superimposed over one another, heating at least one of the areas to a temperature that comprises at least the melting temperature of the solder. The last step comprises joining the superimposed areas to one another. The process employs the flux composition operatively associated with the solder, and in one embodiment the invention comprises a mixture of the flux composition with powdered solder. In another embodiment, the process comprises IMS, C4 and C4NP processes and the solder comprises a lead free solder. The invention also comprises a product produced by the foregoing process or processes.
摘要翻译：本发明涉及包含助焊剂的物质组合物，其中助熔剂基本上由助熔剂和溶剂的组合组成，并且其中助熔剂包括酮酸，例如乙酰丙酸或乙酰基丁酸。助熔剂还可以包含酯酸，或包含酮酸与酯酸的混合物。溶剂包括粘性溶剂与非粘性溶剂的混合物。本发明还涉及一种方法，其包括将至少两个表面焊接在一起，每个表面包括金属区域，焊料可以以任何顺序通过以下步骤粘附到该金属区域：将焊料施加到至少一个金属区域，使金属对准区域，使得它们彼此叠加，将至少一个区域加热至至少包括焊料的熔化温度的温度。最后一步包括将叠加的区域相互连接。该方法使用与焊料可操作地相关联的助熔剂组合物，并且在一个实施方案中，本发明包括焊剂组合物与粉末焊料的混合物。在另一个实施方案中，该方法包括IMS，C4和C4NP方法，焊料包括无铅焊料。本发明还包括通过前述方法或方法生产的产品。

9. 发明申请

US20090298206A1 METHOD AND APPARATUS TO MINIMIZE STRESS DURING REFLOW PROCESS 审中-公开
标题翻译：在反射过程中最小化应力的方法和装置
公开(公告)号：US20090298206A1
公开(公告)日：2009-12-03
申请号：US12127895
申请日：2008-05-28
申请人： Eric Duchesne , Julien Sylvestre
发明人： Eric Duchesne , Julien Sylvestre
IPC分类号： H01L21/66
CPC分类号： H01L24/81 , H01L22/12 , H01L22/20 , H01L24/75 , H01L2224/131 , H01L2224/75272 , H01L2224/759 , H01L2224/81815 , H01L2224/81908 , H01L2924/0001 , H01L2924/00013 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2224/29099 , H01L2224/13099 , H01L2924/00
摘要： Utilizing an appropriately configured laser interferometer, the warpage of a silicon chip can be easily monitored during the solder reflow attachment process in an effort to determine the amount of stress encountered by the chip. Warpage measurements can then be continuously monitored throughout the process and related data can be stored to easily suggest the level of warpage generated by various processing parameters. By dynamically monitoring warpage in conjunction with processing parameters, a correlation can be established between the various parameters chosen, and resulting warpage. Based upon this correlation, the evaluators can easily identify those parameters which produce minimum stress, thus avoiding potential for breakage and damage during reflow operations.
摘要翻译：利用适当配置的激光干涉仪，可以在焊料回流附着过程中容易地监测硅芯片的翘曲，以确定芯片遇到的应力的量。然后可以在整个过程中连续监测翘曲测量，并且可以存储相关数据以容易地建议由各种处理参数产生的翘曲程度。通过结合处理参数动态监测翘曲，可以在所选择的各种参数之间建立相关性，并产生翘曲。基于这种相关性，评估者可以容易地识别产生最小应力的那些参数，从而避免在回流操作期间破裂和损坏的可能性。

10. 发明授权

US08710161B2 Method for transforming a single reactor line 有权
标题翻译：用于转化单个反应器管线的方法
公开(公告)号：US08710161B2
公开(公告)日：2014-04-29
申请号：US12280620
申请日：2007-02-21
申请人： Louis Fouarge , Eric Duchesne
发明人： Louis Fouarge , Eric Duchesne
IPC分类号： C08F2/12 , B21K21/16
CPC分类号： C08F2/01 , B01J8/007 , B01J19/1818 , B01J19/1837 , B01J2208/00176 , B01J2208/00619 , B01J2219/00024 , B01J2219/00031 , B01J2219/00033 , B01J2219/0004 , B01J2219/00094 , B01J2219/00184 , B01J2219/00254 , C08F10/02 , C08F110/02 , C08F210/16 , Y10T29/49716 , C08F2/14 , C08F210/14 , C08F2/001
摘要： The present invention discloses a method for transforming a single reactor line into a double reactor line wherein the existing single reactor line is equipped with a flash tank for separating the solid polymer product from the flash vapor and wherein the vapor is sent to a system of at least two separating columns allowing the separation of its constituents into monomer, diluent and comonomer.
摘要翻译：本发明公开了一种用于将单个反应器管线转化为双重反应器管线的方法，其中现有的单个反应器管线装备有用于将固体聚合物产物与闪蒸蒸气分离的闪蒸罐，并且其中蒸气被送至系统最少两个分离柱允许其组分分离成单体，稀释剂和共聚单体。

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