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    • 3. 发明申请
    • SHARING UNIVERSAL SERIAL BUS ISOCHRONOUS BANDWIDTH BETWEEN MULTIPLE VIRTUAL MACHINES
    • 在多台虚拟机之间共享通用串行总线
    • US20090006702A1
    • 2009-01-01
    • US11768696
    • 2007-06-26
    • Nitin SarangdharBalaji Vembu
    • Nitin SarangdharBalaji Vembu
    • G06F13/14
    • G06F13/14
    • A method and computer readable medium are disclosed. In one embodiment, the method includes enumerating multiple Universal Serial Bus (USB) devices on a computer platform running a multiple virtual machines (VMs). The method also includes assigning each of the USB devices to a VM, wherein each USB device may be assigned to a different VM. The method also includes making each USB device visible only to the VM it is assigned to. The method also includes limiting the bandwidth each of the VMs can schedule its assigned devices within a USB data transfer frame. This will allow all of the VMs to have access to the bandwidth of the frame by avoiding the problem of over-subscription when the schedule is merged.
    • 公开了一种方法和计算机可读介质。 在一个实施例中,该方法包括在运行多个虚拟机(VM)的计算机平台上列举多个通用串行总线(USB)设备。 该方法还包括将每个USB设备分配给VM,其中每个USB设备可被分配给不同的VM。 该方法还包括使每个USB设备仅对其被分配给的VM可见。 该方法还包括限制每个VM的带宽可以在USB数据传输帧内调度其分配的设备。 这将允许所有VM通过避免在合并计划时超额订购的问题来访问帧的带宽。
    • 5. 发明申请
    • DATA ENCRYPTION AND/OR DECRYPTION BY INTEGRATED CIRCUIT
    • 集成电路的数据加密和/或分解
    • US20090323961A1
    • 2009-12-31
    • US12164663
    • 2008-06-30
    • Nitin SarangdharNed SmithVincent Von Bokern
    • Nitin SarangdharNed SmithVincent Von Bokern
    • H04L9/06G06F21/00
    • H04L9/3234G06F12/1408G06F21/72G06F2212/1052H04L9/0833H04L9/0897H04L9/3226H04L9/3263H04L63/0428
    • In an embodiment, an apparatus is provided that may include an integrated circuit to be removably communicatively coupled to at least one storage device. The integrated circuit of this embodiment may be capable of encrypting and/or and decrypting, based at least in part upon a first key, data to be, in at least in part, stored in and/or retrieved from, respectively, at least one region of the at least one storage device. The at least one region and a second key may be associated with at least one access privilege authorized, at least in part, by an administrator. The second key may be stored, at least in part, externally to the at least one storage device. The first key may be obtainable, at least in part, based, at least in part, upon at least one operation involving the second key. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.
    • 在一个实施例中,提供了一种装置,其可以包括可移除地通信地耦合到至少一个存储装置的集成电路。 该实施例的集成电路可以至少部分地基于第一密钥来加密和/或解密数据,该数据至少部分地存储在和/或分别从至少一个 所述至少一个存储设备的区域。 所述至少一个区域和第二密钥可以至少部分由管理员授权的至少一个访问权限相关联。 至少部分地,第二密钥可以存储在至少一个存储设备的外部。 至少部分地,至少部分地基于涉及第二密钥的至少一个操作可获得第一密钥。 当然,在不脱离本实施例的情况下,许多替代,修改和变化是可能的。
    • 6. 发明授权
    • Bus system providing dynamic control of pipeline depth for a multi-agent
computer
    • 总线系统为多代理计算机提供管道深度的动态控制
    • US5948088A
    • 1999-09-07
    • US979740
    • 1997-11-26
    • Nitin SarangdharMichael RhodehamelMatthew Fisch
    • Nitin SarangdharMichael RhodehamelMatthew Fisch
    • G06F13/38G06F13/40G06F13/42G06F9/38
    • G06F13/387G06F13/4027G06F13/4217
    • Each of a plurality of device or agents connected to a computer system bus is provided with a mechanism for unilaterally and dynamically limiting the depth of a pipeline of the bus. Each agent includes a state machine which indicates whether the bus is in a throttled state, a stalled state or a free state. When in a free state, an agent having control of the bus may transmit any number of bus transactions and the depth of the pipeline may therefore increase. In the throttled state, the agent may transmit only a single bus transaction from the throttled state, the state machine always transitions either to the stalled state or to the free state. In the stalled state, no agents may transmit transactions onto the bus and the depth of the pipeline therefore cannot increase and instead may decrease with time as previously issued transactions are drained from the bus. Wired-OR logic is employed for allowing an agent to transmit a state transition signal to all other agents on the bus changing the state of the various state machines. Only a single state transition signal is required to completely control the state of the state machines. By employing wired-OR logic, any particular agent is capable of switching the state machines into a stalled state to prevent new bus transactions from being issued to the bus. In this manner, each agent is capable of unilaterally restricting or limiting the depth of the pipeline. Hardware or software is provided within each agent to control the state machine in a manner such that all state machines remain synchronized with each indicating the same state at substantially the same time.
    • 连接到计算机系统总线的多个设备或代理中的每一个被提供有用于单方面和动态地限制总线管线深度的机构。 每个代理包括状态机,其指示总线是处于节流状态,停止状态还是空闲状态。 当处于空闲状态时,具有总线控制的代理可以发送任何数量的总线事务,并且管道的深度因此可能增加。 在节流状态下,代理可以仅从节流状态传送单个总线事务,状态机总是转换到停止状态或自由状态。 在停滞状态下,没有任何代理可以将事务发送到总线上,因此管道的深度不能增加,而是可以随着时间而减少,因为先前发布的交易从总线中排出。 有线逻辑用于允许代理向总线上的所有其他代理发送状态转换信号,以改变各种状态机的状态。 只需要一个状态转换信号来完全控制状态机的状态。 通过采用有线或逻辑,任何特定的代理能够将状态机切换到停止状态,以防止新总线事务被发送到总线。 以这种方式,每个代理能够单方面限制或限制管道的深度。 在每个代理中提供硬件或软件以以使得所有状态机在基本相同的时间保持与指示相同状态的状态同步的方式来控制状态机。
    • 7. 发明授权
    • Bus agent providing dynamic pipeline depth control
    • 总线代理提供动态管道深度控制
    • US06009477A
    • 1999-12-28
    • US213098
    • 1998-12-17
    • Nitin SarangdharMichael RhodehamelMatthew Fisch
    • Nitin SarangdharMichael RhodehamelMatthew Fisch
    • G06F13/38G06F13/42G06F3/00
    • G06F13/4217G06F13/387
    • Each of a plurality of device or agents connected to a computer system bus is provided with a mechanism for unilaterally and dynamically limiting the depth of a pipeline of the bus. Each agent includes a state machine which indicates whether the bus is in a throttled state, a stalled state or a free state. When in a free state, an agent having control of the bus may transmit any number of bus transactions and the depth of the pipeline may therefore increase. In the throttled state, the agent may transmit only a single bus transaction from the throttled state, the state machine always transitions either to the stalled state or to the free state. In the stalled state, no agents may transmit transactions onto the bus and the depth of the pipeline therefore cannot increase and instead may decrease with time as previously issued transactions are drained from the bus. Wired-OR logic is employed for allowing an agent to transmit a state transition signal to all other agents on the bus changing the state of the various state machines only a single state transition signal is required to completely control the state of the state machines. By employing wired-OR logic, any particular agent is capable of switching the state machines into a stalled state to prevent new bus transactions from being issued to the bus. In this manner, each agent is capable of unilaterally restricting or limiting the depth of the pipeline. Hardware or software is provided within each agent to control the state machine in a manner such that all state machines remain synchronized with each indicating the same state at substantially the same time.
    • 连接到计算机系统总线的多个设备或代理中的每一个被提供有用于单方面和动态地限制总线管线深度的机构。 每个代理包括状态机,其指示总线是处于节流状态,停止状态还是空闲状态。 当处于空闲状态时,具有总线控制的代理可以发送任何数量的总线事务,并且管道的深度因此可能增加。 在节流状态下,代理可以仅从节流状态传送单个总线事务,状态机总是转换到停止状态或自由状态。 在停滞状态下,没有任何代理可以将事务发送到总线上,因此管道的深度不能增加,而是可以随着时间而减少,因为先前发布的交易从总线中排出。 有线逻辑用于允许代理向总线上的所有其他代理发送状态转换信号,改变各种状态机的状态,仅需要单个状态转换信号来完全控制状态机的状态。 通过采用有线或逻辑,任何特定的代理能够将状态机切换到停止状态,以防止新总线事务被发送到总线。 以这种方式,每个代理能够单方面限制或限制管道的深度。 在每个代理中提供硬件或软件以以使得所有状态机在基本相同的时间保持与指示相同状态的状态同步的方式来控制状态机。