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1. 发明授权

US08635415B2 Managing and implementing metadata in central processing unit using register extensions 有权
标题翻译：使用寄存器扩展管理和实施中央处理单元中的元数据
公开(公告)号：US08635415B2
公开(公告)日：2014-01-21
申请号：US12571269
申请日：2009-09-30
申请人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jacob (Koby) Gottlieb
发明人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jacob (Koby) Gottlieb
IPC分类号： G06F12/02 , G06F9/302
CPC分类号： G06F9/3013 , G06F9/30105 , G06F9/30112 , G06F9/32 , G06F9/342 , G06F9/35 , G06F12/1441
摘要： A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
摘要翻译：一组处理器的默认寄存器被扩展到计算机系统的处理器上的元数据寄存器。存储有数据的默认寄存器，而与数据相关的元数据分别存储在元数据寄存器上。

2. 发明申请

US20110078389A1 MANAGING AND IMPLEMENTING METADATA IN CENTRAL PROCESSING UNIT USING REGISTER EXTENSIONS 有权
标题翻译：使用注册扩展管理和实施中央处理单元中的元数据
公开(公告)号：US20110078389A1
公开(公告)日：2011-03-31
申请号：US12571269
申请日：2009-09-30
申请人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jocob Gottlieb
发明人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jocob Gottlieb
IPC分类号： G06F9/30 , G06F12/02 , G06F9/302
CPC分类号： G06F9/3013 , G06F9/30105 , G06F9/30112 , G06F9/32 , G06F9/342 , G06F9/35 , G06F12/1441
摘要： A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
摘要翻译：一组处理器的默认寄存器被扩展到计算机系统的处理器上的元数据寄存器。存储有数据的默认寄存器，而与数据相关的元数据分别存储在元数据寄存器上。

3. 发明授权

US07047394B1 Computer for execution of RISC and CISC instruction sets 有权
标题翻译：用于执行RISC和CISC指令集的计算机
公开(公告)号：US07047394B1
公开(公告)日：2006-05-16
申请号：US09666110
申请日：2000-09-20
申请人： Korbin S. Van Dyke , Paul Campbell , Don Alan Van Dyke
发明人： Korbin S. Van Dyke , Paul Campbell , Don Alan Van Dyke
IPC分类号： G06F9/30
CPC分类号： G06F9/3822 , G06F9/30123 , G06F9/30167 , G06F9/30174 , G06F9/30189 , G06F9/30196
摘要： A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization. The hardware CISC instruction decoder is exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects. The CISC decoder is designed to decode a portion of an instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder. A software emulator is programmed to implement a remainder of the instruction set. The CISC instruction set provides accessibility to only a subset of the registers of the general register file, intermediate results of instructions of the instruction set being stored in registers of the general register file that are inaccessible in the CISC instruction set.
摘要翻译：公开了一种计算机。计算机具有寄存器的通用寄存器文件，RISC指令解码器和CISC指令解码器。 RISC指令解码器被暴露用于执行RISC指令集中的用户状态程序，作为具有固定长度指令的指令集和加载/存储/操作组织。硬件CISC指令解码器被暴露以由CISC指令集中的用户状态程序执行，作为具有可变长度指令的指令集和具有多个副作用的许多指令。 CISC解码器被设计为对计算机的指令集的一部分进行解码，并且将解码的指令递送到被设计为执行RISC指令解码器和CISC指令解码器的输出的指令执行流水线。软件仿真器被编程为实现指令集的剩余部分。 CISC指令集仅提供对通用寄存器文件的寄存器的子集的可访问性，指令集的指令的中间结果存储在通用寄存器堆的寄存器中，该寄存器在CISC指令集中是不可访问的。

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