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1. 发明申请

US20120068891A1 CHIP TO DIELECTRIC WAVEGUIDE INTERFACE FOR SUB-MILLIMETER WAVE COMMUNICATIONS LINK 有权
标题翻译：切割到用于亚微波通信的电介质波导接口
公开(公告)号：US20120068891A1
公开(公告)日：2012-03-22
申请号：US12887323
申请日：2010-09-21
申请人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
发明人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
IPC分类号： H01Q1/24
CPC分类号： H01Q3/44 , H01L23/3107 , H01L23/66 , H01L24/16 , H01L24/48 , H01L24/49 , H01L2223/6677 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2924/00014 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/3011 , H01Q3/26 , H01Q9/0407 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
摘要翻译：在一些开发的互连技术中，例如芯片到芯片的光学互连或金属波导互连，错位可能是一个严重的问题。然而，这里提供了使用片上定向天线（其在亚毫米范围内操作）通过介质波导形成射频（RF）互连的互连。该系统允许不对准，同时提供增加的通信带宽。

2. 发明授权

US09123737B2 Chip to dielectric waveguide interface for sub-millimeter wave communications link 有权
标题翻译：芯片到介质波导接口用于亚毫米波通信链路
公开(公告)号：US09123737B2
公开(公告)日：2015-09-01
申请号：US12887323
申请日：2010-09-21
申请人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
发明人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
IPC分类号： H01Q1/24 , H01L23/66 , H01L23/31 , H01L23/00
CPC分类号： H01Q3/44 , H01L23/3107 , H01L23/66 , H01L24/16 , H01L24/48 , H01L24/49 , H01L2223/6677 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2924/00014 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/3011 , H01Q3/26 , H01Q9/0407 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
摘要翻译：在一些开发的互连技术中，例如芯片到芯片的光学互连或金属波导互连，错位可能是一个严重的问题。然而，这里提供了使用片上定向天线（其在亚毫米范围内操作）通过介质波导形成射频（RF）互连的互连。该系统允许不对准，同时提供增加的通信带宽。

3. 发明授权

US09070703B2 High speed digital interconnect and method 有权
标题翻译：高速数字互连和方法
公开(公告)号：US09070703B2
公开(公告)日：2015-06-30
申请号：US12887270
申请日：2010-09-21
申请人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
发明人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
IPC分类号： H01Q1/24 , H01L23/66 , H01L25/10
CPC分类号： H01L23/66 , H01L25/105 , H01L2223/6677 , H01L2224/48247 , H01L2225/1005 , H01L2924/3011 , H01L2924/00
摘要： In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
摘要翻译：在一些开发的互连技术中，例如芯片到芯片的光学互连或金属波导互连，错位可能是一个严重的问题。然而，这里提供了使用片上定向天线（其在亚毫米范围内操作）通过介质波导形成射频（RF）互连的互连。该系统允许不对准，同时提供增加的通信带宽。

4. 发明申请

US20120068890A1 HIGH SPEED DIGITAL INTERCONNECT AND METHOD 有权
标题翻译：高速数字互连和方法
公开(公告)号：US20120068890A1
公开(公告)日：2012-03-22
申请号：US12887270
申请日：2010-09-21
申请人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
发明人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
IPC分类号： H01Q1/24 , H01Q13/00
CPC分类号： H01L23/66 , H01L25/105 , H01L2223/6677 , H01L2224/48247 , H01L2225/1005 , H01L2924/3011 , H01L2924/00
摘要： In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
摘要翻译：在一些开发的互连技术中，例如芯片到芯片的光学互连或金属波导互连，错位可能是一个严重的问题。然而，这里提供了使用片上定向天线（其在亚毫米范围内操作）通过介质波导形成射频（RF）互连的互连。该系统允许不对准，同时提供增加的通信带宽。

5. 发明授权

US08472437B2 Wireless chip-to-chip switching 有权
标题翻译：无线芯片到芯片切换
公开(公告)号：US08472437B2
公开(公告)日：2013-06-25
申请号：US13026777
申请日：2011-02-14
申请人： Nirmal Chindhu Warke , Srinath Hosur , Martin J. Izzard , Siraj Akhtar , Baher S. Haroun , Marco Corsi
发明人： Nirmal Chindhu Warke , Srinath Hosur , Martin J. Izzard , Siraj Akhtar , Baher S. Haroun , Marco Corsi
IPC分类号： H04L12/50 , H04L12/28 , H04L12/56 , H04Q11/00 , H04B5/00 , H04B7/00
CPC分类号： H04W40/00 , H01Q3/26 , H01Q9/20 , H01Q21/0006 , H01Q21/0037 , H04B7/0617 , H04B17/336 , H04L45/74 , H04L49/3009 , H04L49/40 , H04W40/06 , H04W40/12 , Y02D70/00 , Y02D70/166 , Y02D70/322 , Y02D70/34
摘要： Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface.
摘要翻译：本发明的实施例提供了一种用于电子电路中芯片到芯片通信的系统和方法。路由器或交换机在输入端口ASIC处接收数据包。输入端口ASIC或路由ASIC上的路由表用于根据数据包中的报头信息识别目标端口ASIC。使用在波导或无线接口上传输的毫米波信号，将数据分组从输入端口ASIC发送到目标端口ASIC。

6. 发明申请

US20110199972A1 Wireless Chip-to-Chip Switching 有权
标题翻译：无线芯片到芯片切换
公开(公告)号：US20110199972A1
公开(公告)日：2011-08-18
申请号：US13026777
申请日：2011-02-14
申请人： Nirmal Chindhu Warke , Srinath Hosur , Martin J. Izzard , Siraj Akhtar , Baher S. Haroun , Marco Corsi
发明人： Nirmal Chindhu Warke , Srinath Hosur , Martin J. Izzard , Siraj Akhtar , Baher S. Haroun , Marco Corsi
IPC分类号： H04W40/00
CPC分类号： H04W40/00 , H01Q3/26 , H01Q9/20 , H01Q21/0006 , H01Q21/0037 , H04B7/0617 , H04B17/336 , H04L45/74 , H04L49/3009 , H04L49/40 , H04W40/06 , H04W40/12 , Y02D70/00 , Y02D70/166 , Y02D70/322 , Y02D70/34
摘要： Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface.
摘要翻译：本发明的实施例提供了一种用于电子电路中芯片到芯片通信的系统和方法。路由器或交换机在输入端口ASIC处接收数据包。输入端口ASIC或路由ASIC上的路由表用于根据数据包中的报头信息识别目标端口ASIC。使用在波导或无线接口上传输的毫米波信号，将数据分组从输入端口ASIC发送到目标端口ASIC。

7. 发明申请

US20120098069A1 NEUTRALIZATION CAPACITANCE IMPLEMENTATION 有权
标题翻译：中和电容实现
公开(公告)号：US20120098069A1
公开(公告)日：2012-04-26
申请号：US12911488
申请日：2010-10-25
申请人： Siraj Akhtar
发明人： Siraj Akhtar
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/088
摘要： Neutralization capacitances are commonly employed to compensate for the Miller effect; however, at higher frequencies, the parasitic inductance introduced in the interconnect can affect the neutralization. Here, a layout has been provided where a MOS capacitor is merged with a complementary transistor. By having this merged device, the layout is compact and reduces interconnect area, which reduces the effects of parasitic inductance at higher frequencies (i.e., millimeter wave or terahertz). This layout can also be used to implement linearity enhancement schemes.
摘要翻译：中和电容通常用于补偿米勒效应; 然而，在较高的频率下，引入到互连中的寄生电感可以影响中和。这里，已经提供了一种布置，其中MOS电容器与互补晶体管合并。通过具有这种合并器件，布局紧凑并且减小了互连面积，这降低了在较高频率（即，毫米波或太赫兹）处的寄生电感的影响。该布局也可用于实现线性增强方案。

8. 发明申请

US20120086505A1 SWITCHING CORE LAYOUT 有权
标题翻译：切换核心布局
公开(公告)号：US20120086505A1
公开(公告)日：2012-04-12
申请号：US12899390
申请日：2010-10-06
申请人： Siraj Akhtar
发明人： Siraj Akhtar
IPC分类号： H01L25/00
CPC分类号： H03D7/1458 , H03D7/1433 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0019 , H03D2200/0082
摘要： Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.
摘要翻译：传统上，混频器已经围绕输入信号对称布置，这导致了由于本机振荡器信号的自混合或馈通引起的问题。然而，这里，混频器的布置已经改变，以便大体上避免本地振荡器信号的自混合。特别地，切换核心中的晶体管根据所接收的本地振荡器信号的部分被合并。这又导致承载本地振荡器信号的不同部分的导体被分离（或不具有任何交叉），以便通常消除本机振荡器信号的自混合或馈通。使用这种安排实现的复杂IQ混音器可从改进的边带抑制和镜像抑制中获益。

9. 发明授权

US08471302B2 Neutralization capacitance implementation 有权
标题翻译：中和电容实现
公开(公告)号：US08471302B2
公开(公告)日：2013-06-25
申请号：US12911488
申请日：2010-10-25
申请人： Siraj Akhtar
发明人： Siraj Akhtar
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/088
摘要： Neutralization capacitances are commonly employed to compensate for the Miller effect; however, at higher frequencies, the parasitic inductance introduced in the interconnect can affect the neutralization. Here, a layout has been provided where a MOS capacitor is merged with a complementary transistor. By having this merged device, the layout is compact and reduces interconnect area, which reduces the effects of parasitic inductance at higher frequencies (i.e., millimeter wave or terahertz). This layout can also be used to implement linearity enhancement schemes.
摘要翻译：中和电容通常用于补偿米勒效应; 然而，在较高的频率下，引入到互连中的寄生电感可以影响中和。这里，已经提供了一种布置，其中MOS电容器与互补晶体管合并。通过具有这种合并器件，布局紧凑并且减小了互连面积，这降低了在较高频率（即，毫米波或太赫兹）处的寄生电感的影响。该布局也可用于实现线性增强方案。

10. 发明申请

US20120242403A1 SWITCHING CORE LAYOUT 有权
公开(公告)号：US20120242403A1
公开(公告)日：2012-09-27
申请号：US13490264
申请日：2012-06-06
申请人： Siraj Akhtar
发明人： Siraj Akhtar
IPC分类号： H01L25/00
CPC分类号： H03D7/1458 , H03D7/1433 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0019 , H03D2200/0082
摘要： Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.

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