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1. 发明授权

US08426269B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08426269B2
公开(公告)日：2013-04-23
申请号：US13289096
申请日：2011-11-04
申请人： Baek-Mann Kim
发明人： Baek-Mann Kim
IPC分类号： H01L21/8242
CPC分类号： H01L21/28525 , H01L21/76877 , H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns.
摘要翻译：一种制造半导体器件的方法包括通过在具有掩埋栅极的衬底中进行离子注入形成用于位线接触（BLC）的接合区域和用于存储节点接触（SNC）的接合区域; 形成具有开口以暴露接合区域的第一绝缘图案; 形成缓冲层以填充开口; 在填充所述开口之后，在所述第一绝缘图案上形成第二绝缘图案，其中所述第二绝缘图案具有用于在所述缓冲层的位于所述SNC的接合区域之上的区域中暴露所述缓冲层的开口; 并形成SNC以填充第二绝缘图案的开口。

2. 发明授权

US08445369B2 Method for fabricating semiconductor device 有权
公开(公告)号：US08445369B2
公开(公告)日：2013-05-21
申请号：US13244136
申请日：2011-09-23
申请人： Baek-Mann Kim
发明人： Baek-Mann Kim
IPC分类号： H01L21/265
CPC分类号： H01L21/28525 , H01L21/76877 , H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns.

3. 发明申请

US20100164118A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE INCLUDING METAL CONTACT 审中-公开
标题翻译：用于制造包括金属接触的半导体器件的方法
公开(公告)号：US20100164118A1
公开(公告)日：2010-07-01
申请号：US12483558
申请日：2009-06-12
申请人： Baek-Mann Kim , Seung-Jin Yeom , Jik-Ho Cho
发明人： Baek-Mann Kim , Seung-Jin Yeom , Jik-Ho Cho
IPC分类号： H01L23/522 , H01L21/60
CPC分类号： H01L27/10894 , H01L21/76804 , H01L21/76816 , H01L21/76895 , H01L27/10885 , H01L27/10888 , Y10T29/49204
摘要： A method for fabricating a semiconductor device includes: forming first landing metal contacts over a substrate; forming a plurality of bit lines over the first landing metal contacts, the bit lines insulated from the first landing metal contacts by an inter-layer insulation layer; forming second landing metal through-hole contacts passing between adjacent bit lines to be coupled to the first landing metal contacts; forming metal contacts over the second landing metal contacts; and forming a metal line over the metal contacts.
摘要翻译：一种制造半导体器件的方法包括：在衬底上形成第一接地金属接触; 在所述第一着陆金属触点上形成多个位线，所述位线通过层间绝缘层与所述第一着陆金属触点绝缘; 形成第二着陆金属通孔触点，其通过相邻的位线之间，以耦合到所述第一着陆金属触点; 在第二着陆金属触点上形成金属触点; 并在金属触点上形成金属线。

4. 发明授权

US08053341B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08053341B2
公开(公告)日：2011-11-08
申请号：US12939453
申请日：2010-11-04
申请人： Baek-Mann Kim
发明人： Baek-Mann Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/28525 , H01L21/76877 , H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns.
摘要翻译：一种制造半导体器件的方法包括通过在具有掩埋栅极的衬底中进行离子注入形成用于位线接触（BLC）的接合区域和用于存储节点接触（SNC）的接合区域; 形成具有开口以暴露接合区域的第一绝缘图案; 形成缓冲层以填充开口; 在填充所述开口之后，在所述第一绝缘图案上形成第二绝缘图案，其中所述第二绝缘图案具有用于在所述缓冲层的位于所述SNC的接合区域之上的区域中暴露所述缓冲层的开口; 并形成SNC以填充第二绝缘图案的开口。

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