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1. 发明申请

US20150369748A1 FILM EDGE DETECTING METHOD AND FILM EDGE DETECTING DEVICE 有权
标题翻译：薄膜边缘检测方法和薄膜边缘检测装置
公开(公告)号：US20150369748A1
公开(公告)日：2015-12-24
申请号：US14548997
申请日：2014-11-20
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Shoukun WANG , Huibin GUO , Yuchun FENG , Liangliang LI , Xiaoxiang ZHANG , Zongjie GUO
IPC分类号： G01N21/84
CPC分类号： G01N21/8422 , G01B11/00 , G01B11/14 , G01B11/24 , G01N21/8851 , G01N2201/10
摘要： The present invention provides a film edge detecting method and a film edge detecting device. The film edge detecting method is used for detecting a film edge of a film layer formed on a substrate, the film layer comprises a patterned film layer, the method includes: forming at least one scale pattern in the patterned film layer, a film edge of the patterned film layer corresponding to an edge of the scale pattern; obtaining a patterned film edge indication value of the edge of the scale pattern; and obtaining a second distance, which is a distance between the film edge of the non-patterned film layer and a corresponding edge of the substrate, based on the non-patterned film edge indication value and a preset reference value of the corresponding edge of the substrate.
摘要翻译：本发明提供一种胶片边缘检测方法和胶片边缘检测装置。膜边缘检测方法用于检测在基板上形成的膜层的膜边缘，该膜层包括图案化膜层，该方法包括：在图案化膜层中形成至少一个标尺图案，所述图案化膜层对应于所述标尺图案的边缘; 获得刻度图案的边缘的图案化胶片边缘指示值; 并且基于未图案化的膜边缘指示值和相对于所述基板的相应边缘的预设参考值，获得作为所述非图案化膜层的膜边缘与所述基板的相应边缘之间的距离的第二距离基质。

2. 发明申请

US20150318362A1 THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管及其制造方法，阵列基板及其制造方法
公开(公告)号：US20150318362A1
公开(公告)日：2015-11-05
申请号：US14406892
申请日：2014-06-18
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Shoukun WANG , Huibin GUO , Yuchun FENG , Xiaowei LIU , Zongjie GUO
IPC分类号： H01L29/417 , H01L27/12 , H01L29/66 , H01L29/786 , H01L21/283 , H01L21/027
CPC分类号： H01L29/41733 , H01L21/0273 , H01L21/283 , H01L27/1222 , H01L27/1288 , H01L29/66742 , H01L29/66765 , H01L29/786
摘要： A thin film transistor and manufacturing method thereof, an array substrate (1) comprising the thin film transistor and manufacturing method thereof. The method of manufacturing the thin film transistor comprises forming an active layer (4) and a source-drain electrode layer (5), forming a photoresist layer (6) on the source-drain electrode layer (5) and forming a pattern of the photoresist layer by a pattern process; etching the source-drain electrode layer (5) by using the pattern of the photoresist layer as a mask to form a pattern of the source-drain electrode layer including a source electrode and a drain electrode; and removing the photoresist, then etching the active layer (4) by using the pattern of the source-drain electrode layer as a mask to form a pattern of the active layer. The method of manufacturing the thin film transistor and the array substrate can prevent or decrease the possibility of the region of the active layer between the source electrode and the drain electrode in the thin film transistor being polluted by organics, thereby improve the electrical performance of the thin film transistor.
摘要翻译：一种薄膜晶体管及其制造方法，包括薄膜晶体管的阵列基板（1）及其制造方法。制造薄膜晶体管的方法包括形成有源层（4）和源极 - 漏极电极层（5），在源极 - 漏极电极层（5）上形成光刻胶层（6）并形成光刻胶层通过图案处理; 通过使用光致抗蚀剂层的图案作为掩模来蚀刻源极 - 漏极电极层（5），以形成包括源电极和漏电极的源极 - 漏极电极层的图案; 并去除光致抗蚀剂，然后通过使用源极 - 漏极电极层的图案作为掩模来蚀刻有源层（4）以形成有源层的图案。制造薄膜晶体管和阵列基板的方法可以防止或减少薄膜晶体管中的源电极和漏电极之间的有源层的区域被有机物污染的可能性，从而提高薄膜晶体管的电性能薄膜晶体管。

3. 发明申请

US20180090377A1 ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE 审中-公开
公开(公告)号：US20180090377A1
公开(公告)日：2018-03-29
申请号：US15521079
申请日：2016-09-07
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Shoukun WANG , Huibin GUO , Yuchun FENG , Liangliang LI
IPC分类号： H01L21/77 , H01L21/3213 , H01L27/14
CPC分类号： H01L21/77 , H01L21/32139 , H01L27/12 , H01L27/124 , H01L27/1259 , H01L27/14
摘要： An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, a signal line disposed on the base substrate, an extinction layer disposed between the base substrate and the signal line, the extinction layer being configured to reduce an ambient light when the array substrate is located on a light exiting side. An orthographic projection of the signal line in a plane of the base substrate is coincided with an orthographic projection of the extinction layer in the plane of the base substrate.

4. 发明申请

US20150348999A1 Manufacturing Method of an Array Substrate 有权
标题翻译：阵列基板的制造方法
公开(公告)号：US20150348999A1
公开(公告)日：2015-12-03
申请号：US14519480
申请日：2014-10-21
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Huibin GUO , Shoukun WANG , Xiaowei LIU , Yuchun FENG , Zongjie GUO
IPC分类号： H01L27/12 , H01L29/45 , H01L29/49
CPC分类号： H01L27/1262 , H01L27/1288 , H01L29/458 , H01L29/4908
摘要： Provided is a manufacturing method of an array substrate with an etching stop layer. The method includes: forming a pattern including a gate, a gate line and a common electrode line on a substrate through a first patterning process; forming a gate insulation layer, an active layer film and an etching stop layer through a second patterning process; wherein, the etching stop layer corresponds to a gap between a source and a drain which are to be formed, and a via hole exposing the common electrode line is formed above the common electrode line; forming at least an active layer, a pattern including source, drain and data line and a protection layer through a third patterning process; wherein, the protection layer exposes a part of the drain; and forming at least a pixel electrode through a fourth patterning process; wherein, the pixel electrode is electrically connected with the drain.
摘要翻译：提供了具有蚀刻停止层的阵列基板的制造方法。该方法包括：通过第一图案化工艺在衬底上形成包括栅极，栅极线和公共电极线的图案; 通过第二图案化工艺形成栅极绝缘层，有源层膜和蚀刻停止层; 其中，所述蚀刻停止层对应于要形成的源极和漏极之间的间隙，并且在所述公共电极线上方形成暴露所述公共电极线的通孔; 通过第三图案化工艺形成至少有源层，包括源极，漏极和数据线的图案和保护层; 其中，所述保护层暴露所述漏极的一部分; 以及通过第四图案化工艺形成至少一个像素电极; 其中，像素电极与漏极电连接。

5. 发明申请

US20180364530A1 ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS 审中-公开
公开(公告)号：US20180364530A1
公开(公告)日：2018-12-20
申请号：US15521339
申请日：2016-11-02
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Shoukun WANG , Liangliang LI , Yuchun FENG , Huibin GUO
IPC分类号： G02F1/1362 , G02F1/1368 , H01L27/12
CPC分类号： G02F1/136209 , G02F1/136204 , G02F1/136286 , G02F1/1368 , G02F2001/136231 , G02F2202/22 , H01L27/1262 , H01L27/1288
摘要： This present disclosure provides an array substrate, a manufacturing method thereof, and a display apparatus, aiming at solving the issue of light reflection on the array substrates and improving the display effects of display apparatuses. The array substrate includes a transparent substrate; a plurality of components disposed on a first side of the transparent substrate; and a shielding pattern, disposed on a second side of the transparent substrate, and configured to shield light reflected from a surface of at least one of the plurality of components.

6. 发明申请

US20150329432A1 Method for Preparing Polycrystalline Metal Oxide Pattern 有权
标题翻译：制备多晶金属氧化物图案的方法
公开(公告)号：US20150329432A1
公开(公告)日：2015-11-19
申请号：US14526777
申请日：2014-10-29
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Liangliang LI , Zongjie GUO , Huibin GUO , Shoukun WANG , Yuchun FENG , Xiaowei LIU
IPC分类号： C04B41/91 , C04B41/53 , C04B41/00
CPC分类号： H01L21/02691 , C04B41/0036 , C04B41/0072 , C04B41/5353 , C04B41/91 , H01L21/02422 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/02686
摘要： Disclosed is a method for preparing a polycrystalline metal oxide pattern, characterized by comprising: annealing a predetermined region of an amorphous metal oxide film by laser, so as to convert the amorphous metal oxide in the predetermined region into a polycrystalline metal oxide; and etching the amorphous metal oxide outside of the predetermined region so as to remove it. By the method according to the present invention, firstly, the predetermined region of an amorphous metal oxide film is annealed by laser so as to convert the amorphous metal oxide into a polycrystalline metal oxide, and then, the amorphous metal oxide outside of the predetermined region is etched away, thereby a polycrystalline metal oxide pattern is formed. The method for preparing a polycrystalline metal oxide pattern according to the present invention is simple, and can effectively shorten the production period and save production costs.
摘要翻译：公开了一种制备多晶金属氧化物图案的方法，其特征在于包括：通过激光对预定区域的非晶金属氧化物膜进行退火，以将预定区域中的非晶态金属氧化物转化成多晶金属氧化物; 并且在预定区域外蚀刻非晶态金属氧化物以便将其去除。根据本发明的方法，首先，通过激光对非晶金属氧化物膜的预定区域进行退火，以将非晶金属氧化物转化为多晶金属氧化物，然后在预定区域外部的非晶态金属氧化物被蚀刻掉，从而形成多晶金属氧化物图案。根据本发明的多晶金属氧化物图案的制备方法简单，可以有效缩短生产周期，节省生产成本。

7. 发明申请

US20180026056A1 ARRAY SUBSTRATE, PREPARATION METHOD THEREOF AND DISPLAY DEVICE 审中-公开
公开(公告)号：US20180026056A1
公开(公告)日：2018-01-25
申请号：US15657413
申请日：2017-07-24
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Liangliang LI , Huibin GUO , Shoukun WANG , Yuchun FENG , Yao LIU
IPC分类号： H01L27/12
CPC分类号： H01L27/1262 , G02F1/136286 , G02F2001/13629 , G02F2001/136295 , G02F2201/38 , H01L21/02123 , H01L21/0217 , H01L21/02203 , H01L21/02263 , H01L21/76829 , H01L27/1218 , H01L27/124 , H01L51/5284
摘要： The present invention provides an array substrate comprising a substrate, a metal conductive film layer, and an anti-reflective film layer located between the substrate and the metal conductive film layer, and a method for manufacturing the same, as well as a display device. The method comprises step S1: forming an anti-reflective film layer on a substrate by adjusting the reaction power and/or reactive gas flow during the formation of film by the chemical vapor deposition process; and step S2: forming a metal conductive film layer on the substrate finished in step S1. Through the preparation method of the array substrate, the anti-reflective film layer can have a sand-like granulation structure, such that light reflected from the metal conductive film layer can be blocked, thereby weakening or avoiding the light reflected from the surface of the metal conductive film layer, further improving the display effect of the array substrate.

8. 发明申请

US20160349584A1 ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL 有权
标题翻译：阵列基板，其制造方法和显示面板
公开(公告)号：US20160349584A1
公开(公告)日：2016-12-01
申请号：US14354186
申请日：2013-12-03
申请人： Boe Technology Group Co., Ltd , Beijing Boe Display Technology Co.,Ltd
发明人： Xi CHEN , Yuchun FENG , Jianfeng YUAN , Linlin WANG
IPC分类号： G02F1/1362 , G02F1/1368 , H01L27/12
CPC分类号： G02F1/136259 , G02F1/136286 , G02F1/1368 , G02F2001/136263 , H01L27/124 , H01L27/1244
摘要： An array substrate, a manufacturing method thereof and a display panel are disclosed. The array substrate includes: a base substrate, gate scanning lines, a gate-insulating layer, an active layer, data lines, a passivation layer, and pixel electrodes; the array substrate further includes: a bridge structure and a connection line corresponding to each data line; the bridge structure is located on the passivation layer and is provided in a same layer as the pixel electrodes; each connection line is located on the base substrate and is connected with the data line, through the bridge structure in an LED region and in a region under a scribe line of a counter substrate. Therefore the problem of defective display caused by breakage of data lines can be solved, and the display effect of a liquid crystal display device can be improved.
摘要翻译：公开了阵列基板，其制造方法和显示面板。阵列基板包括：基底基板，栅极扫描线，栅极绝缘层，有源层，数据线，钝化层和像素电极; 阵列基板还包括：桥结构和对应于每条数据线的连接线; 桥结构位于钝化层上并且设置在与像素电极相同的层中; 每个连接线位于基底基板上，并通过LED区域中的桥结构和相对基板的划线下方的区域与数据线连接。因此，可以解决由于数据线的破损引起的不良显示的问题，并且可以提高液晶显示装置的显示效果。

9. 发明申请

US20160139421A1 PARALLAX BARRIER AND FABRICATING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE 审中-公开
标题翻译： PARALLAX BARRIER及其制作方法，显示面板和显示设备
公开(公告)号：US20160139421A1
公开(公告)日：2016-05-19
申请号：US14436763
申请日：2014-09-23
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Huibin GUO , Zhenyu ZHANG , Shoukun WANG , Liangliang LI , Yuchun FENG
IPC分类号： G02B27/22 , G02F1/1333 , G02F1/1341 , G02F1/1343
CPC分类号： G02B27/2214 , G02B27/225 , G02F1/133345 , G02F1/1341 , G02F1/134309 , G02F1/1345
摘要： The embodiments of the present invention disclose a parallax bather and a fabricating method thereof. The parallax barrier comprises a first transparent conducting layer (35), a second transparent conducting layer (36), and an insulating layer (37) between the first transparent conducting layer (35) and the second transparent conducting layer (36). The first transparent conductive layer (35) is formed into a plurality of signal electrode lines (350), and the second transparent conductive layer (36) is formed into a plurality of common electrode lines (360). The signal electrode lines (350) and the common electrode lines (360) are arranged alternately, and the common electrode lines (360) are located in a gap between adjacent signal electrode lines (350) with the insulating layer (37) in between.
摘要翻译：本发明的实施例公开了一种视差沐浴器及其制造方法。视差屏障包括第一透明导电层（35），第二透明导电层（36）和在第一透明导电层（35）和第二透明导电层（36）之间的绝缘层（37）。第一透明导电层（35）形成为多条信号电极线（350），第二透明导电层（36）形成为多条公共电极线（360）。信号电极线（350）和公共电极线（360）交替配置，公共电极线（360）位于相邻的信号电极线（350）之间的间隔和绝缘层（37）之间。

10. 发明申请

US20150236128A1 THIN-FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, TFT ARRAY SUBSTRATE AND DISPLAY DEVICE 有权
标题翻译：薄膜晶体管及其制造方法，TFT阵列基板和显示装置
公开(公告)号：US20150236128A1
公开(公告)日：2015-08-20
申请号：US14466218
申请日：2014-08-22
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Shoukun WANG , Huibin GUO , Xiaowei LIU , Yuchun FENG , Zongjie GUO
IPC分类号： H01L29/66 , H01L29/786 , H01L27/12 , H01L21/265
CPC分类号： H01L21/02694 , H01L21/02592 , H01L21/2253 , H01L21/265 , H01L21/26513 , H01L27/1214 , H01L27/127 , H01L29/66742 , H01L29/66765 , H01L29/786 , H01L29/78669 , H01L29/78696
摘要： The present invention discloses a method for manufacturing a thin-film transistor, comprising the steps of: forming a semiconductor active layer, and a doped semiconductor active layer; forming a source-drain metal layer; forming a channel region; and implanting ions for lowering the TFT leakage current into the surface of the semiconductor active layer in the channel region via ion implantation after forming the channel region. The invention further relates to a thin-film transistor, a TFT array substrate and a display device. The invention has the following beneficial effects: by implanting ions for lowering the TFT leakage current into the channel region, the electrical performance of a TFT may be improved, and the thickness of a semiconductor active layer in a channel region may be changed controllably.
摘要翻译：本发明公开了一种制造薄膜晶体管的方法，包括以下步骤：形成半导体有源层和掺杂的半导体有源层; 形成源极 - 漏极金属层; 形成通道区域; 以及在形成沟道区域之后通过离子注入注入用于将TFT漏电流降低到沟道区中的半导体有源层的表面中的离子。本发明还涉及薄膜晶体管，TFT阵列基板和显示装置。本发明具有以下有益效果：通过注入用于将TFT漏电流降低到沟道区域中的离子，可以提高TFT的电性能，并且可以可控地改变沟道区中半导体活性层的厚度。

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