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1. 发明授权

US07710767B2 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US07710767B2
公开(公告)日：2010-05-04
申请号：US11969326
申请日：2008-01-04
申请人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多个第一行中的对应的第一行和存储单元的第二端连接到多条第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

2. 发明授权

US08248842B2 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US08248842B2
公开(公告)日：2012-08-21
申请号：US12732990
申请日：2010-03-26
申请人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.
摘要翻译：一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多个第一行的对应的第一行和存储单元的第二端连接到多条第二行的对应的第二行; 偏置电路，用于将所选择的第二行的第二行偏置为参考电压和未选择的第二行至第一电压; 以及本地字线地址解码器将对应于第一电压的参考电压或泵浦电压施加到偏置电路。

3. 发明申请

US20100246248A1 MEMORY CELL ARRAY BIASING METHOD AND A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：存储单元阵列偏移方法和半导体存储器件
公开(公告)号：US20100246248A1
公开(公告)日：2010-09-30
申请号：US12732990
申请日：2010-03-26
申请人： BEAK-HYUNG CHO , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： BEAK-HYUNG CHO , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C11/00 , G11C8/08
CPC分类号： G11C13/0023 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.
摘要翻译：一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多个第一行的对应的第一行和存储单元的第二端连接到多条第二行的对应的第二行; 偏置电路，用于将所选择的第二行的第二行偏置为参考电压和未选择的第二行至第一电压; 以及本地字线地址解码器将对应于第一电压的参考电压或泵浦电压施加到偏置电路。

4. 发明申请

US20080165575A1 MEMORY CELL ARRAY BIASING METHOD AND A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：存储单元阵列偏移方法和半导体存储器件
公开(公告)号：US20080165575A1
公开(公告)日：2008-07-10
申请号：US11969326
申请日：2008-01-04
申请人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C11/00 , G11C8/08 , G11C7/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多个第一行中的对应的第一行和存储单元的第二端连接到多条第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

5. 发明授权

US07317655B2 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US07317655B2
公开(公告)日：2008-01-08
申请号：US11327967
申请日：2006-01-09
申请人： Beak-Hyung Cho , Du-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Du-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C8/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：提供了一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件。半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多条第一线路中的相应第一线路，而存储器单元的第二端子连接到多个第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

6. 发明申请

US20060164896A1 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US20060164896A1
公开(公告)日：2006-07-27
申请号：US11327967
申请日：2006-01-09
申请人： Beak-Hyung Cho , Du-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Du-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C7/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：提供了一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件。半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多条第一线路中的相应第一线路，而存储器单元的第二端子连接到多个第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

7. 发明授权

US07542356B2 Semiconductor memory device and method for reducing cell activation during write operations 有权
标题翻译：用于在写入操作期间减少电池激活的半导体存储器件和方法
公开(公告)号：US07542356B2
公开(公告)日：2009-06-02
申请号：US11790146
申请日：2007-04-24
申请人： Kwang-Jin Lee , Sang-Beom Kang , Hyung-Rok Oh , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Kwang-Jin Lee , Sang-Beom Kang , Hyung-Rok Oh , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C7/06
CPC分类号： G11C13/0069 , G11C7/06 , G11C7/1006 , G11C13/0004 , G11C2013/0076 , G11C2211/5647
摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.
摘要翻译：本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

8. 发明申请

US20080101131A1 Semiconductor memory device and method for reducing cell activation during write operations 有权
标题翻译：用于在写入操作期间减少电池激活的半导体存储器件和方法
公开(公告)号：US20080101131A1
公开(公告)日：2008-05-01
申请号：US11790146
申请日：2007-04-24
申请人： Kwang-Jin Lee , Sang-Beom Kang , Hyung-Rok Oh , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Kwang-Jin Lee , Sang-Beom Kang , Hyung-Rok Oh , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C7/06
CPC分类号： G11C13/0069 , G11C7/06 , G11C7/1006 , G11C13/0004 , G11C2013/0076 , G11C2211/5647
摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.
摘要翻译：本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

9. 发明授权

US07391644B2 Phase-changeable memory device and read method thereof 有权
标题翻译：相变存储器件及其读取方法
公开(公告)号：US07391644B2
公开(公告)日：2008-06-24
申请号：US11605212
申请日：2006-11-29
申请人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.
摘要翻译：公开了一种可变相存储器件和读取数据的相关方法。存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。每个存储单元包括相位可变材料和连接到位线的二极管。高压电路从电源提供高电压。预充电电路将位线充电至电源电压后，将位线升高至高电压。偏置电路通过高电压向位线提供读取电流。读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

10. 发明授权

US06982913B2 Data read circuit for use in a semiconductor memory and a memory thereof 有权
标题翻译：用于半导体存储器的数据读取电路及其存储器
公开(公告)号：US06982913B2
公开(公告)日：2006-01-03
申请号：US10943300
申请日：2004-09-17
申请人： Hyung-Rok Oh , Woo-Yeong Cho , Choong-Keun Kwak
发明人： Hyung-Rok Oh , Woo-Yeong Cho , Choong-Keun Kwak
IPC分类号： G11C7/00
CPC分类号： G11C13/004 , G11C7/06 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2013/0054 , G11C2207/005
摘要： A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.
摘要翻译：提供了一种用于具有存储单元阵列的半导体存储器件中的数据读取电路和方法。该电路包括：选择器，用于响应于地址信号选择存储单元阵列内的单位单元; 夹紧单元，用于响应于钳位控制信号，将具有用于读取操作的电平的钳位电压提供给所选择的单位单元的位线; 预充电单元，用于响应于在预充电模式中的第一状态的控制信号而将感测节点预充电到具有电源电平的电压，并且响应于位线在位线处减小的电流量补偿在数据感测模式中的第二状态的控制信号; 以及感测放大器单元，用于将感测节点的电平与参考电平进行比较，并且用于感测存储在所选择的单位单元中的数据。

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