专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060119437A1 Voltage controlled clock synthesizer 有权
标题翻译：电压时钟合成器
公开(公告)号：US20060119437A1
公开(公告)日：2006-06-08
申请号：US11270957
申请日：2005-11-10
申请人： Axel Thomsen , Yunteng Huang , Jerrell Hein , Derrick Wei
发明人： Axel Thomsen , Yunteng Huang , Jerrell Hein , Derrick Wei
IPC分类号： H03L7/00
CPC分类号： H03L7/0898 , H03L1/022 , H03L1/026 , H03L7/095 , H03L7/0992 , H03L7/197 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/50 , H04J3/0688
摘要： A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.
摘要翻译：电压控制时钟合成器包括接收定时参考信号的锁相环（PLL）电路，提供振荡器输出信号的可控振荡器电路，例如VCO，以及耦合到振荡器输出信号的反馈分频器电路。振荡器输出信号的频率部分地根据用于产生确定反馈分频器电路的分频比的第一数字控制信号的存储值来确定。存在于电压控制输入端的控制电压根据由存储的值确定的频率调整振荡器输出信号的频率。控制电压被转换为第二数字信号，并用于与所存储的值组合确定第一数字控制信号。

2. 发明申请

US20060119402A1 Multi-frequency clock synthesizer 有权
标题翻译：多频时钟合成器
公开(公告)号：US20060119402A1
公开(公告)日：2006-06-08
申请号：US11270954
申请日：2005-11-10
申请人： Axel Thomsen , Yunteng Huang , Jerrell Hein , Michael Petrowski
发明人： Axel Thomsen , Yunteng Huang , Jerrell Hein , Michael Petrowski
IPC分类号： H03B21/00
CPC分类号： H03L7/23 , H03L7/0898 , H03L7/197 , H03L7/1976
摘要： A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.
摘要翻译：锁相环（PLL）电路包括用于接收定时参考信号的输入端，耦合以接收定时参考信号的相位检测器电路，根据相位检测器电路的输出控制的可控振荡器电路，以及反馈分配器电路具有耦合到相位检测器的输出端和耦合到可控振荡器电路的输入端。锁相环电路根据频率选择机构耦合到输出具有任意频率关系的多个输出信号中的一个，所述频率选择机构包括一个或多个输入端，用于控制所述频率选择机构的分频比反馈分频电路。频率选择机构选择多个存储值中的一个。选择的存储值至少部分地控制反馈分频器电路的分频比，从而提供能够在彼此具有任意关系的输出频率之间进行选择的引脚可编程器件。

3. 发明申请

US20070146083A1 CALIBRATION OF OSCILLATOR DEVICES 审中-公开
标题翻译：振荡器器件校准
公开(公告)号：US20070146083A1
公开(公告)日：2007-06-28
申请号：US11681941
申请日：2007-03-05
申请人： Jerrell Hein , Axel Thomsen
发明人： Jerrell Hein , Axel Thomsen
IPC分类号： H03L7/00
CPC分类号： H03L1/022 , H03L1/026 , H03L7/095 , H03L7/0992 , H03L7/1976 , H03L7/235 , H03L2207/50
摘要： A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.
摘要翻译：通过提供校准时钟来校准具有诸如数字控制振荡器等可控振荡器的SAW的晶体谐振装置的时钟装置。利用锁相环产生一个或多个校正因子，使PLL锁定到校准时钟。然后将一个或多个校正因子存储在非易失性存储器中。

4. 发明授权

US07187241B2 Calibration of oscillator devices 有权
标题翻译：振荡器设备的校准
公开(公告)号：US07187241B2
公开(公告)日：2007-03-06
申请号：US10675543
申请日：2003-09-30
申请人： Jerrell Hein , Axel Thomsen
发明人： Jerrell Hein , Axel Thomsen
IPC分类号： H03L7/00
CPC分类号： H03L1/022 , H03L1/026 , H03L7/095 , H03L7/0992 , H03L7/1976 , H03L7/235 , H03L2207/50
摘要： A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.
摘要翻译：通过提供校准时钟来校准具有诸如数字控制振荡器等可控振荡器的SAW的晶体谐振装置的时钟装置。利用锁相环产生一个或多个校正因子，使PLL锁定到校准时钟。然后将一个或多个校正因子存储在非易失性存储器中。

5. 发明授权

US08471629B2 Providing automatic power control for a power amplifier 有权
标题翻译：为功率放大器提供自动功率控制
公开(公告)号：US08471629B2
公开(公告)日：2013-06-25
申请号：US13173791
申请日：2011-06-30
申请人： Axel Thomsen , Zhongda Wang , Sai Chu Wong , Yunteng Huang
发明人： Axel Thomsen , Zhongda Wang , Sai Chu Wong , Yunteng Huang
IPC分类号： H03F1/14 , H03G3/20
CPC分类号： H03G3/34 , H03G3/3042
摘要： A power control circuit is coupled to receive a feedback signal from a power amplifier (PA) and generate a control signal to control a variable gain amplifier (VGA) coupled to an input to the PA based on the feedback signal. The power control circuit may include, in one embodiment, a mute circuit to generate a mute signal to be provided to the VGA when the control signal is less than a first level and a clamp circuit to clamp a control voltage used to generate the control signal from exceeding a threshold level.
摘要翻译：功率控制电路被耦合以从功率放大器（PA）接收反馈信号，并产生控制信号，以根据反馈信号控制耦合到PA的输入的可变增益放大器（VGA）。在一个实施例中，功率控制电路可以包括静音电路，以在控制信号小于第一电平时产生要提供给VGA的静音信号，以及钳位电路来钳位用于产生控制信号的控制电压超过阈值水平。

6. 发明授权

US07288998B2 Voltage controlled clock synthesizer 有权
标题翻译：电压时钟合成器
公开(公告)号：US07288998B2
公开(公告)日：2007-10-30
申请号：US11270957
申请日：2005-11-10
申请人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Derrick C. Wei
发明人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Derrick C. Wei
IPC分类号： H03L7/00
CPC分类号： H03L7/0898 , H03L1/022 , H03L1/026 , H03L7/095 , H03L7/0992 , H03L7/197 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/50 , H04J3/0688
摘要： A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.
摘要翻译：电压控制时钟合成器包括接收定时参考信号的锁相环（PLL）电路，提供振荡器输出信号的可控振荡器电路，例如VCO，以及耦合到振荡器输出信号的反馈分频器电路。振荡器输出信号的频率部分地根据用于产生确定反馈分频器电路的分频比的第一数字控制信号的存储值来确定。存在于电压控制输入端的控制电压根据由存储的值确定的频率调整振荡器输出信号的频率。控制电压被转换为第二数字信号，并用于与所存储的值组合确定第一数字控制信号。

7. 发明授权

US06970030B1 Dual phased-locked loop structure having configurable intermediate frequency and reduced susceptibility to interference 失效
标题翻译：双相锁相环结构具有可配置的中频和降低的干扰敏感性
公开(公告)号：US06970030B1
公开(公告)日：2005-11-29
申请号：US10676626
申请日：2003-10-01
申请人： Yunteng Huang , Ligang Zhang , Axel Thomsen
发明人： Yunteng Huang , Ligang Zhang , Axel Thomsen
IPC分类号： G06F1/04 , G06F7/68 , H03L7/183 , H03L7/23
CPC分类号： G06F7/68 , H03L7/183 , H03L7/23
摘要： A PLL function may be implemented as a dual-loop structure having a first PLL circuit which generates an intermediate signal from the reference signal, and a second PLL circuit which generates an output signal from the intermediate signal. The intermediate signal frequency is preferably chosen at a value in which potential interference signals do not have much energy. The first loop preferably has low bandwidth to provide good input jitter attenuation, while second loop preferably has higher bandwidth to reduce phase noise of the output signal. The circuit preferably provides for a choice of several different intermediate frequencies to allow use where different intermediate frequencies may exist in each system. Moreover, in a system having two such dual-loop PLL circuits, each can be configured with a different intermediate frequency, so that interference from one to the other is reduced.
摘要翻译： PLL功能可以实现为具有从参考信号产生中间信号的第一PLL电路的双回路结构，以及从中间信号产生输出信号的第二PLL电路。中间信号频率优选地被选择为其中潜在的干扰信号没有太多能量的值。第一环路优选具有低带宽以提供良好的输入抖动衰减，而第二环路优选地具有较高带宽以减少输出信号的相位噪声。该电路优选地提供几种不同中频的选择，以允许在每个系统中可能存在不同中频的应用。此外，在具有两个这样的双回路PLL电路的系统中，每个都可以配置有不同的中频，从而减少了从一个到另一个的干扰。

8. 发明申请

US20090039968A1 DUAL LOOP ARCHITECTURE USEFUL FOR A PROGRAMMABLE CLOCK SOURCE AND CLOCK MULTIPLIER APPLICATIONS 有权
标题翻译：双循环架构可用于可编程时钟源和时钟多路复用器应用
公开(公告)号：US20090039968A1
公开(公告)日：2009-02-12
申请号：US12249457
申请日：2008-10-10
申请人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein
发明人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein
IPC分类号： H03L7/07
CPC分类号： H03L1/022 , H03L1/026 , H03L7/095 , H03L7/0992 , H03L7/1976 , H03L7/235 , H03L2207/50
摘要： A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.
摘要翻译：第一锁相环（PLL）电路包括用于从振荡器接收定时参考信号的输入端，提供振荡器输出信号的可控振荡器电路和多模反馈分频器电路。第二控制回路电路通过选择电路可选地耦合，以将数字控制值（M）提供给第一回路电路的多模反馈分配器电路，从而控制振荡器输出信号。当第二控制回路被耦合以将控制值提供给反馈分配器电路时，根据在分频器电路处的振荡器输出信号和耦合到第二控制回路电路的参考信号之间的检测到差异来确定控制值。当第二控制环路电路不耦合以控制第一PLL电路时，第一PLL电路接收数字控制值以控制反馈分频器的分频比，数字控制值至少部分地根据存储的控制存储在非易失性存储器中的值，所存储的控制值对应于振荡器输出信号的期望频率。

9. 发明授权

US07436227B2 Dual loop architecture useful for a programmable clock source and clock multiplier applications 有权
标题翻译：双循环架构可用于可编程时钟源和时钟乘法器应用
公开(公告)号：US07436227B2
公开(公告)日：2008-10-14
申请号：US10878218
申请日：2004-06-28
申请人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein
发明人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein
IPC分类号： H03L7/06
CPC分类号： H03L1/022 , H03L1/026 , H03L7/095 , H03L7/0992 , H03L7/1976 , H03L7/235 , H03L2207/50
摘要： A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.
摘要翻译：第一锁相环（PLL）电路包括用于从振荡器接收定时参考信号的输入端，提供振荡器输出信号的可控振荡器电路和多模反馈分频器电路。第二控制回路电路通过选择电路可选地耦合，以将数字控制值（M）提供给第一回路电路的多模反馈分配器电路，从而控制振荡器输出信号。当第二控制回路被耦合以将控制值提供给反馈分配器电路时，根据在分频器电路处的振荡器输出信号和耦合到第二控制回路电路的参考信号之间的检测到差异来确定控制值。当第二控制环路电路不耦合以控制第一PLL电路时，第一PLL电路接收数字控制值以控制反馈分频器的分频比，数字控制值至少部分地根据存储的控制存储在非易失性存储器中的值，所存储的控制值对应于振荡器输出信号的期望频率。

10. 发明授权

US07295077B2 Multi-frequency clock synthesizer 有权
标题翻译：多频时钟合成器
公开(公告)号：US07295077B2
公开(公告)日：2007-11-13
申请号：US11270954
申请日：2005-11-10
申请人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Michael Petrowski, III
发明人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Michael Petrowski, III
IPC分类号： H03B21/00
CPC分类号： H03L7/23 , H03L7/0898 , H03L7/197 , H03L7/1976
摘要： A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.
摘要翻译：锁相环（PLL）电路包括用于接收定时参考信号的输入端，耦合以接收定时参考信号的相位检测器电路，根据相位检测器电路的输出控制的可控振荡器电路，以及反馈分配器电路具有耦合到相位检测器的输出端和耦合到可控振荡器电路的输入端。锁相环电路根据频率选择机构耦合到输出具有任意频率关系的多个输出信号中的一个，所述频率选择机构包括一个或多个输入端，用于控制所述频率选择机构的分频比反馈分频电路。频率选择机构选择多个存储值中的一个。选择的存储值至少部分地控制反馈分频器电路的分频比，从而提供能够在彼此具有任意关系的输出频率之间进行选择的引脚可编程器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式