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1. 发明授权

US5329170A Balanced circuitry for reducing inductive noise of external chip interconnections 失效
标题翻译：平衡电路，用于减少外部芯片互连的电感噪声
公开(公告)号：US5329170A
公开(公告)日：1994-07-12
申请号：US166342
申请日：1993-12-13
申请人： Attilio J. Rainal
发明人： Attilio J. Rainal
IPC分类号： H01L21/60 , H01L23/50 , H01L23/64 , H01L25/065 , H01L25/10 , H01L25/00 , H03B1/00
CPC分类号： H01L23/645 , H01L23/50 , H01L24/49 , H01L25/0655 , H01L2223/6611 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2224/73265 , H01L2224/85207 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/0106 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111
摘要： Ground noise associated with lead inductance in electronic systems containing multiple lead integrated circuits is substantially reduced by including, for each chip driver lead that carries a signal, a complementary lead which carries the the inverse of that signal. These balanced pairs are continued not only in the wire bonds and lead frame of the integrated circuit, but also through any connecting assembly such as a printed wiring board or multichip module to the associated balanced chip receivers.
摘要翻译：与包含多个引线集成电路的电子系统中的引线电感相关联的接地噪声通过对携带信号的每个芯片驱动器引线包括承载该信号的反相的互补引线而大大减少。这些平衡对不仅在集成电路的引线框架和引线框架中，而且还通过诸如印刷线路板或多芯片模块的任何连接组件连接到相关联的平衡芯片接收器。

2. 发明授权

US4498122A High-speed, high pin-out LSI chip package 失效
标题翻译：高速，高引脚的LSI芯片封装
公开(公告)号：US4498122A
公开(公告)日：1985-02-05
申请号：US454197
申请日：1982-12-29
申请人： Attilio J. Rainal
发明人： Attilio J. Rainal
IPC分类号： H01L23/52 , H01L23/12 , H01L23/50 , H01L23/538 , H01L23/66 , H05K7/10 , H05K1/14
CPC分类号： H05K7/1084 , H01L23/50 , H01L23/66 , H01L2924/0002 , H01L2924/3011
摘要： A high-speed, high pin-out chip carrier package (10) for interconnecting at least one LSI or VLSI chip to a circuit pack is disclosed. The package includes a ground plane (19), a power plane (20), and at least one signal layer (15, 16, 17, 18) containing plural conductors therethrough. Layers (85) of dielectric material separate adjacent conductive layers, (15, 16, 17, 18, 19, 20). By controlling, in design, the width of each signal conductor and its distance to the nearest ground (19) or power plane (20), the package is impedance-matched to the circuit pack. Plural plated-through holes (21) are disposed through the package for electrically interconnecting the signal conductors, the ground plane (19), and the power plane (20) to the circuit pack, and are arranged in a pattern to reduce inductive noise.
摘要翻译：公开了一种用于将至少一个LSI或VLSI芯片与电路板互连的高速，高引脚输出芯片载体封装（10）。封装包括接地平面（19），电源平面（20）以及包含多个导体的至少一个信号层（15,16,17,18）。电介质材料层（85）将相邻导电层（15,16,17,18,19,20）分开。通过在设计中控制每个信号导体的宽度及其距离最近的地面（19）或电源平面（20）的距离，封装与电路板阻抗匹配。通过封装件设置多个电镀通孔（21），用于将信号导体，接地平面（19）和电源平面（20）电连接到电路板，并且以图案布置以减小感应噪声。

3. 发明授权

US4157612A Method for improving the transmission properties of a connectorized flat cable interconnection assembly 失效
标题翻译：一种用于改善连接器扁平电缆互连组件的传输特性的方法
公开(公告)号：US4157612A
公开(公告)日：1979-06-12
申请号：US864337
申请日：1977-12-27
申请人： Attilio J. Rainal
发明人： Attilio J. Rainal
IPC分类号： H01R12/70 , H01R13/6471 , H01R13/658 , H01R13/6585 , H01R13/6596 , H01R11/32
CPC分类号： H01R13/6471 , H01R13/6585 , H01R13/6596 , Y10T29/49123 , Y10T29/49222
摘要： A method is disclosed for improving the transmission properties of balanced and unbalanced connectorized flat cable interconnection assemblies. In accordance with the method, a first set of generally parallel flat cable conductors are terminated on a first mapped set of connector contacts such that all conductors are connectable to a source of ground potential. A second set of generally parallel flat cable conductors are terminated on a second mapped set of connector contacts such that the odd-numbered conductors are connectable to a source of ground potential and the even-numbered conductors are connectable to a plurality of signal sources. The termination of flat cable conductors in accordance with this method also results in an improvement in the packaging density of pluggably interconnectable circuits.
摘要翻译：公开了一种用于改善平衡和不平衡的连接器扁平电缆互连组件的传输特性的方法。根据该方法，第一组大致平行的扁平电缆导体终止在第一映射的连接器触点组上，使得所有导体可连接到地电位源。第二组大致平行的扁平电缆导体终止在第二映射的连接器触头组上，使得奇数编号的导体可连接到接地电位源，偶数导体可连接到多个信号源。根据该方法的扁平电缆导体的端接也导致可插拔的互连电路的封装密度的改善。

4. 发明授权

US5767995A System and methods for assessing the suitability of analog lasers for broadband access applications 失效
标题翻译：用于评估模拟激光器适用于宽带接入应用的系统和方法
公开(公告)号：US5767995A
公开(公告)日：1998-06-16
申请号：US596899
申请日：1996-03-13
申请人： Attilio J. Rainal , Venkataraman Swaminathan
发明人： Attilio J. Rainal , Venkataraman Swaminathan
IPC分类号： H04B10/155 , H04J14/02
CPC分类号： H04B10/504 , H04B10/541 , H04B10/58 , H04J14/0298
摘要： A system and method for predicting the ratio of the strength of the carrier signal to the strength of nonlinear distortion (C/NLD) generated by a communications laser is disclosed. The method jointly evaluates the individual distortion components arising from laser clipping and from inherent laser P-I nonlinearity. According to the method, the laser P-I curve is measured with high precision to quantify the P-I nonlinearity. Various derivatives of the P-I curve are determined and then utilized to calculate C/NLD as a function of a communications network parameter such as the optical modulation index per channel or rms modulation index. Based on this information, the laser can be identified in terms of its sensitivity to RF drive variations in the field. Lasers can be tagged, etc., depending on their C/NLD sensitivity. In this manner, a laser having a C/NLD ratio appropriate for the requirements of a broadband transmission network, such as a SCM CATV system, can be selected and installed in such a system.
摘要翻译：公开了一种用于预测载波信号的强度与通信激光器产生的非线性失真强度（C / NLD）的比率的系统和方法。该方法联合评估由激光削波产生的各个失真分量和固有激光P-I非线性。根据该方法，以高精度测量激光P-I曲线以量化P-I非线性。确定P-I曲线的各种导数，然后用于计算作为通信网络参数的函数的C / NLD，例如每个信道的光调制指数或均方根调制指数。基于该信息，可以根据其对现场RF驱动变化的灵敏度来识别激光。激光器可以被标记等，这取决于它们的C / NLD灵敏度。以这种方式，可以选择并安装具有适合于诸如SCM CATV系统的宽带传输网络的要求的C / NLD比率的激光器。

5. 发明授权

US5519353A Balanced driver circuit for eliminating inductive noise 失效
标题翻译：平衡驱动电路，用于消除电感噪声
公开(公告)号：US5519353A
公开(公告)日：1996-05-21
申请号：US895767
申请日：1992-06-09
申请人： Attilio J. Rainal
发明人： Attilio J. Rainal
IPC分类号： H03F1/26 , H03K19/003 , H03K19/013 , H03K19/018 , H03K19/086 , H04L25/02 , H03K17/16 , H03M1/00
CPC分类号： H03K19/00361
摘要： A balanced driver circuit which essentially eliminates inductive noise without a power dissipation penalty is disclosed. The balanced driver circuit is similar to a conventional balanced driver circuit however the circuit is impedance matched at both ends and has resistors connected in series with the outputs of the emitter followers in the chip. The resistors are equal in value to a termination resistor less the output impedance of the emitter followers. The impedance between the pair of signal leads, referred to as the primary and secondary leads is equal to the sum of the termination resistors. The current traversing the secondary lead has the same amplitude, but the opposite sign as the current traversing the primary lead. Thus, there is negligible current return through the common ground leads.
摘要翻译：公开了一种平衡的驱动电路，其基本上消除了没有功率损耗的电感噪声。平衡驱动器电路类似于传统的平衡驱动器电路，然而电路在两端是阻抗匹配的，并且具有与芯片中的发射极跟随器的输出串联的电阻器。电阻值与终端电阻的值相等，减少了发射极跟随器的输出阻抗。被称为初级和次级引线的一对信号引线之间的阻抗等于终端电阻的和。穿过次级引线的电流具有相同的幅度，但与穿过主引线的电流相反。因此，通过共同的引线可以忽略电流回报。

6. 发明授权

US5502644A Process and apparatus for auditing crosstalk and characteristic impedances of printed wiring boards 失效
标题翻译：用于审核印刷电路板串扰和特性阻抗的工艺和设备
公开(公告)号：US5502644A
公开(公告)日：1996-03-26
申请号：US225012
申请日：1994-04-07
申请人： Eric A. Hamilton , Attilio J. Rainal , Jere C. Shank
发明人： Eric A. Hamilton , Attilio J. Rainal , Jere C. Shank
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A tool for designing the conductors into a PWB includes an audit arrangement for auditing or analyzing crosstalk between electrical conductors to be entered into the PWB. This crosstalk audit may be performed as soon as the initial design is created and before actual manufacture of the PWB. It is operative to identify crosstalk problem areas and to identify impedance mismatches. In particular the audit process defines conduction paths into conduction nets conduction nets are selected one at a time for evaluation and simulated as having an idle current condition. Nearby conduction nets are simulated as being driven in an active condition. The response of the idle network is used to derive a plurality of crosstalk parameters which are used to determine the crosstalk effect on the net under test.
摘要翻译：用于将导体设计成PWB的工具包括用于审核或分析要输入到PWB的电导线之间的串扰的审核装置。一旦创建初始设计，并且在实际制造PWB之前，可以执行该串扰审核。识别串扰问题区域并识别阻抗失配是有效的。特别地，审计过程将传导路径定义为传导网络，一次一个地选择传导网络进行评估，并将其模拟为具有空闲电流条件。附近的传导网被模拟为在活动状态下被驱动。空闲网络的响应用于导出多个串扰参数，这些参数用于确定被测网络上的串扰效应。

7. 发明授权

US5304856A Article comprising a balanced driver circuit with less power dissipation than conventional circuit 失效
标题翻译：文章包括平衡的驱动电路，功耗比常规电路低
公开(公告)号：US5304856A
公开(公告)日：1994-04-19
申请号：US992514
申请日：1992-12-17
申请人： Attilio J. Rainal
发明人： Attilio J. Rainal
IPC分类号： H03K19/003 , H03K19/018 , H04L25/02 , H01P5/00
CPC分类号： H03K19/00353
摘要： By on-chip modification of a conventional balanced driver to yield special voltage levels, the power dissipation of a balanced, terminated transmission line circuit can be reduced by 50% or more relative to a conventional balanced driver or 25% or more relative to a conventional unbalanced driver. This reduction in power dissipation not only applies to point-to-point interconnections but also applies to bused interconnections. The low power balanced driver circuit can be implemented using ECL, BiCMOS, GaAs and CMOS technologies and no modifications are needed to the associated differential line receiver. Thus, the significant benefits of balanced interconnections, namely reduced crosstalk, increased noise immunity, and elimination of ground noise can be realized with a significant reduction in power dissipation.
摘要翻译：通过对常规平衡驱动器进行片上修改以产生特殊的电压电平，相对于传统的平衡驱动器，平衡端接的传输线路电路的功耗可以降低50％或更多，相对于传统的平衡驱动器不平衡的司机功耗的这种降低不仅适用于点对点互连，而且也适用于有源互连。低功率平衡驱动器电路可以使用ECL，BiCMOS，GaAs和CMOS技术实现，并且不需要对相关的差分线路接收器进行修改。因此，能够显着降低功耗，可以实现平衡互连的显着优点，即降低串扰，提高噪声抗扰度和消除地面噪声。

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