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    • 2. 发明申请
    • DISPLAY DEVICE AND DISPLAY METHOD
    • 显示装置和显示方法
    • US20100097525A1
    • 2010-04-22
    • US12530990
    • 2008-03-11
    • Atsushi Mino
    • Atsushi Mino
    • H04N5/445
    • G09G3/003G02F1/1323G02F1/133524G02F2201/52G09G3/3611G09G2340/0457H04N13/31
    • Provided are a cheap display device and a display method that are capable of preventing loss of high-frequency component during generation of a video signal from a source signal while at the same time securing continuity of pixel data.The display device includes a display portion 7 capable of displaying distinct videos on a common screen in a plurality of viewing directions and a video signal generating portion 300 for generating video signals by carrying out compression processing of video source signals for the viewing directions at predetermined compression rates. The video signal generating portion 300 generates new color components by using color components of a plurality of adjacent pixels aligned in a predetermined direction among pixels corresponding to the video source signals, and generates each of the video signals on the basis of a new pixel composed of the generated color components.
    • 提供了一种廉价的显示装置和显示方法,其能够防止在从源信号生成视频信号的同时保持像素数据的连续性的同时损失高频分量。 显示装置包括能够在多个观看方向上的公共屏幕上显示不同视频的显示部分7以及用于通过以预定压缩对观看方向执行视频源信号的压缩处理来产生视频信号的视频信号产生部分300 价格。 视频信号产生部分300通过使用与视频源信号相对应的像素之中的与预定方向对齐的多个相邻像素的颜色分量来生成新的颜色分量,并且基于由 生成的颜色成分。
    • 3. 发明申请
    • Video signal processing device
    • 视频信号处理装置
    • US20090128692A1
    • 2009-05-21
    • US12292250
    • 2008-11-14
    • Atsushi Mino
    • Atsushi Mino
    • H04N7/01
    • H04N5/126H03L7/07H03L7/0805
    • Provided is a video signal processing device capable of judging the viability of phase locking at a PLL circuit and, in accordance with the judgment, automatically switching between the PLL circuit and a DLL circuit to use to generate a sampling clock of an input analog video signal, the device including an AD converter for AD converting an analog video signal, and a clock signal generating circuit for supplying a clock signal to the AD converter. The clock signal generating circuit includes: a PLL circuit for generating a first clock signal on the basis of a horizontal synchronous signal acquired from the analog video signal; a DLL circuit for generating a second clock signal on the basis of a composite synchronous signal acquired from the analog video signal; and a clock selecting portion for selecting and outputting either the first clock signal or the second clock signal on the basis of output of a PLL-dedicated phase comparator.
    • 提供一种视频信号处理装置,其能够判断PLL电路的相位锁定的可行性,并且根据判断自动切换PLL电路和DLL电路以用于生成输入模拟视频信号的采样时钟 该装置包括用于AD转换模拟视频信号的AD转换器,以及用于向AD转换器提供时钟信号的时钟信号发生电路。 时钟信号发生电路包括:PLL电路,用于根据从模拟视频信号获取的水平同步信号产生第一时钟信号; DLL电路,用于根据从模拟视频信号获取的复合同步信号产生第二时钟信号; 以及时钟选择部分,用于基于PLL专用相位比较器的输出来选择和输出第一时钟信号或第二时钟信号。
    • 4. 发明授权
    • Video signal processing device
    • 视频信号处理装置
    • US08233092B2
    • 2012-07-31
    • US12292250
    • 2008-11-14
    • Atsushi Mino
    • Atsushi Mino
    • H03M1/12
    • H04N5/126H03L7/07H03L7/0805
    • Provided is a video signal processing device capable of judging the viability of phase locking at a PLL circuit and, in accordance with the judgment, automatically switching between the PLL circuit and a DLL circuit to use to generate a sampling clock of an input analog video signal, the device including an AD converter for AD converting an analog video signal, and a clock signal generating circuit for supplying a clock signal to the AD converter. The clock signal generating circuit includes: a PLL circuit for generating a first clock signal on the basis of a horizontal synchronous signal acquired from the analog video signal; a DLL circuit for generating a second clock signal on the basis of a composite synchronous signal acquired from the analog video signal; and a clock selecting portion for selecting and outputting either the first clock signal or the second clock signal on the basis of output of a PLL-dedicated phase comparator.
    • 提供一种视频信号处理装置,其能够判断PLL电路的相位锁定的可行性,并且根据判断自动切换PLL电路和DLL电路以用于生成输入模拟视频信号的采样时钟 该装置包括用于AD转换模拟视频信号的AD转换器,以及用于向AD转换器提供时钟信号的时钟信号发生电路。 时钟信号发生电路包括:PLL电路,用于根据从模拟视频信号获取的水平同步信号产生第一时钟信号; DLL电路,用于根据从模拟视频信号获取的复合同步信号产生第二时钟信号; 以及时钟选择部分,用于基于PLL专用相位比较器的输出来选择和输出第一时钟信号或第二时钟信号。
    • 6. 发明申请
    • DISPLAY CONTROL DEVICE AND DISPLAY DEVICE
    • 显示控制装置和显示装置
    • US20100091190A1
    • 2010-04-15
    • US12521845
    • 2008-01-16
    • Atsushi Mino
    • Atsushi Mino
    • H04N5/445
    • G09G3/3611G02B5/003G02B26/08G02B27/2214G02F1/133524G06F3/14G09G3/003G09G3/3648G09G5/04G09G2320/0242H04N13/31
    • Provided is a display control device and a display device that are capable of preventing degradation of image quality caused by video dot crawling when the display device provides for different displays corresponding to a plurality of viewing directions and is set to display the same video signals when viewed from the viewing directions. A display control device 4 includes a video signal generating portion 42 for generating video signals corresponding to different viewing directions from a plurality of source signals so that the display control device 4 outputs the video signals to a display portion 11 capable of displaying different videos on a common screen in the different viewing directions. The video signal generating portion 42 includes a delay processing portion 424 for, when the source signals for the videos displayed in the different viewing directions are the same, delaying a scan line of one video signal by a predetermined line number relative to a scan line of another video signal.
    • 提供了一种显示控制装置和显示装置,当显示装置提供与多个观看方向相对应的不同显示时,能够防止由视频点爬行引起的图像质量的劣化,并且被设置为在观看时显示相同的视频信号 从观看方向。 显示控制装置4包括用于从多个源信号产生对应于不同观看方向的视频信号的视频信号产生部分42,使得显示控制装置4将视频信号输出到能够在显示部分11上显示不同视频的显示部分11 普通屏幕在不同的观看方向。 视频信号产生部分42包括延迟处理部分424,用于当在不同观看方向上显示的视频的源信号相同时,将一个视频信号的扫描线相对于扫描线的扫描线延迟预定行号 另一个视频信号。