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1. 发明申请

US20140282321A1 SYSTEM AND METHOD FOR A HYBRID CLOCK DOMAIN CROSSING VERIFICATION 有权
标题翻译：混合时域交叉验证的系统和方法
公开(公告)号：US20140282321A1
公开(公告)日：2014-09-18
申请号：US13864082
申请日：2013-04-16
申请人： ATRENTA, INC.
发明人： Mohamed Shaker Sarwary , Maher Mneimneh , Mohammad H. Movahed-Ezazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/62 , G06F2217/84
摘要： A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded after review. Assertions and monitors are generated by this process to capture the assumptions and check partially covered properties by formal analysis. A dynamic simulation is run using a testbench, the generated assertions and the monitors. The static verification and dynamic verification processes may be repeated until a satisfactory coverage is obtained. A system, such as a computer aided design (CAD) system, is configured to perform CDC verification of the IC design. The system may generate assertions and monitors to then run a simulation and determine coverage. Results are then reiterated through the system back to the static CDC verification.
摘要翻译：混合时钟域交叉（CDC）验证的方法包括接收设计或集成电路（IC）设计约束。执行静态CDC验证，包括结构和功能验证。检查结果，并进行明确或隐含的假设进行签收验证。不完整的形式分析结果在审查后被丢弃。断言和监视器由此过程产生，以通过正式分析来捕获假设并检查部分覆盖的属性。使用测试台，生成的断言和监视器运行动态模拟。可以重复静态验证和动态验证过程，直到获得令人满意的覆盖。诸如计算机辅助设计（CAD）系统的系统被配置为执行IC设计的CDC验证。系统可以生成断言和监视器，然后运行模拟并确定覆盖。然后通过系统将结果重新发送到静态CDC验证。

2. 发明授权

US08788993B2 Computer system for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design 有权
标题翻译：用于生成用于片上系统（SoC）设计的分层分析的IP核的集成统一视图的计算机系统
公开(公告)号：US08788993B2
公开(公告)日：2014-07-22
申请号：US13961758
申请日：2013-08-07
申请人： Atrenta, Inc.
发明人： Sridhar Gangadharan , Mohammad H. Movahed-Ezazi , Shaker Sarwary , Fadi Maamari , Subir Chandra Ray
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： In order to realize some of the advantages described above, there is provided a computer system for verification of an intellectual property (IP) core in a system-on-chip (SoC). The system generates a plurality of verification specific abstracted views of the IP core, each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view of the IP-core is generated.
摘要翻译：为了实现上述的一些优点，提供了一种用于验证片上系统（SoC）中的知识产权（IP）核心的计算机系统。该系统生成IP核的多个验证特定抽象视图，多个验证特定抽象视图中的每一个具有多个验证特定属性，该视图在每个抽象视图的输入/输出（I / O）接口处 IP核产生了IP核的统一抽象视图。

3. 发明授权

US08984457B2 System and method for a hybrid clock domain crossing verification 有权
标题翻译：用于混合时钟域交叉验证的系统和方法
公开(公告)号：US08984457B2
公开(公告)日：2015-03-17
申请号：US13864082
申请日：2013-04-16
申请人： Atrenta, Inc.
发明人： Mohamed Shaker Sarwary , Maher Mneimneh , Mohammad H. Movahed-Ezazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/62 , G06F2217/84
摘要： A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded after review. Assertions and monitors are generated by this process to capture the assumptions and check partially covered properties by formal analysis. A dynamic simulation is run using a testbench, the generated assertions and the monitors. The static verification and dynamic verification processes may be repeated until a satisfactory coverage is obtained. A system, such as a computer aided design (CAD) system, is configured to perform CDC verification of the IC design. The system may generate assertions and monitors to then run a simulation and determine coverage. Results are then reiterated through the system back to the static CDC verification.
摘要翻译：混合时钟域交叉（CDC）验证的方法包括接收设计或集成电路（IC）设计约束。执行静态CDC验证，包括结构和功能验证。检查结果，并进行明确或隐含的假设进行签收验证。不完整的形式分析结果在审查后被丢弃。断言和监视器由此过程产生，以通过正式分析来捕获假设并检查部分覆盖的属性。使用测试台，生成的断言和监视器运行动态模拟。可以重复静态验证和动态验证过程，直到获得令人满意的覆盖。诸如计算机辅助设计（CAD）系统的系统被配置为执行IC设计的CDC验证。系统可以生成断言和监视器，然后运行模拟并确定覆盖。然后通过系统将结果重新发送到静态CDC验证。

4. 发明授权

US08677295B1 Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design 有权
标题翻译：使用净活动和xor技术的半导体设计的顺序时钟门控，包括已经选通的管道设计
公开(公告)号：US08677295B1
公开(公告)日：2014-03-18
申请号：US14083109
申请日：2013-11-18
申请人： Atrenta, Inc.
发明人： Solaiman Rahim , Mohammad H. Movahed-Ezazi
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505 , G06F17/5045
摘要： The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.
摘要翻译：电路设计过程需要减少大型集成电路和片上系统设计的功耗的方法。这通常通过引入时钟门控的过程来实现，从而启用或禁用与电路内的特定功能块相关联的触发器。然而，电路中的这种变化需要综合和验证，以确保设计和操作的正确性，因为顺序时钟选通动态地改变状态功能。因此，有必要定义适应于设计中这种动态变化的合成方法。根据实施例，顺序时钟门控方法使用异或技术来克服现有技术方法的缺陷。

5. 发明申请

US20140101630A1 COMPUTER SYSTEM FOR GENERATING AN INTEGRATED AND UNIFIED VIEW OF IP-CORES FOR HIERARCHICAL ANALYSIS OF A SYSTEM ON CHIP (SOC) DESIGN 有权
标题翻译：用于生成用于芯片（SOC）设计系统的分层分析的IP网络的集成和统一视图的计算机系统
公开(公告)号：US20140101630A1
公开(公告)日：2014-04-10
申请号：US13961758
申请日：2013-08-07
申请人： Atrenta, Inc.
发明人： Sridhar Gangadharan , Mohammad H. Movahed-Ezazi , Shaker Sarwary , Fadi Maamari , Subir Chandra Ray
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： In order to realize some of the advantages described above, there is provided a computer system for verification of an intellectual property (IP) core in a system-on-chip (SoC). The system generates a plurality of verification specific abstracted views of the IP core, each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view'of the IP-core is generated.
摘要翻译：为了实现上述的一些优点，提供了一种用于验证片上系统（SoC）中的知识产权（IP）核心的计算机系统。该系统生成IP核的多个验证特定抽象视图，多个验证特定抽象视图中的每一个具有多个验证特定属性，该视图在每个抽象视图的输入/输出（I / O）接口处 IP核产生了IP核的统一抽象视图。

6. 发明申请

US20140282322A1 SYSTEM AND METHOD FOR FILTRATION OF ERROR REPORTS RESPECTIVE OF STATIC AND QUASI-STATIC SIGNALS WITHIN AN INTEGRATED CIRCUIT DESIGN 审中-公开
标题翻译：在集成电路设计中过滤静态和静态信号的错误报告的系统和方法
公开(公告)号：US20140282322A1
公开(公告)日：2014-09-18
申请号：US13872303
申请日：2013-04-29
申请人： ATRENTA, INC.
发明人： Mohamed Shaker Sarwary , Maher Mneimneh , Paras Mal Jain , Mohammad H. Movahed-Ezazi , Jean P. Binois
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5022 , G06F2217/84
摘要： A system and method identify potentially static and/or quasi-static signals within an integrated circuit (IC), or portion thereof. Static and quasi-static signals may be identified in a design description of the IC by any one or more of: (1) a fan-out size exceeding some threshold, (2) a toggle frequency in a simulation trace that is below some threshold, and (3) a signal name that appears in a list accessed from the memory. Identification of static and quasi-static signals is performed, typically, as part of a verification process in order to flag cases where the verification system would otherwise indicate an error (e.g., at a clock domain crossing). Identifying a signal of the IC as being static or quasi-static improves the quality of results of verification and makes it easier for a prospective user to concentrate on actual rather than spurious issues reported during verification.
摘要翻译：系统和方法在集成电路（IC）或其一部分内识别潜在的静态和/或准静态信号。静态和准静态信号可以在IC的设计描述中通过以下任何一个或多个来识别：（1）超出某个阈值的扇出尺寸，（2）模拟轨迹中的触发频率低于某个阈值，和（3）出现在从存储器访问的列表中的信号名称。典型地，作为验证过程的一部分来执行静态和准静态信号的识别，以便标记验证系统否则将指示错误（例如，在时钟域交叉处）的情况。将IC的信号识别为静态或准静态可提高验证结果的质量，并使潜在用户更容易集中在验证期间报告的实际而不是虚假问题。

7. 发明授权

US08739087B1 System and method for large multiplexer identification and creation in a design of an integrated circuit 有权
标题翻译：用于集成电路设计中的大型多路复用器识别和创建的系统和方法
公开(公告)号：US08739087B1
公开(公告)日：2014-05-27
申请号：US13756083
申请日：2013-01-31
申请人： Atrenta, Inc.
发明人： Tien-Chien Lee , Saurabh Verma , Satrajit Pal , Chandra Manglani , Jitendra Kumar , Mohammad H. Movahed-Ezazi
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： In the process of designing an integrated circuit (IC), it is often the case that a functional description is converted into multiplexers. In some cases it would be more efficient to combine two or more multiplexers into a larger multiplexer to identify potential design problems in the original register transfer level (RTL). Such early detection can prevent routing congestion problem that would be too expensive to fix later. A large multiplexer is defined as a multiplexer having a number of inputs and control signals that is above a predetermined threshold. When such a multiplexing functionality is detected that function may be replaced in the circuit with a large multiplexer that would be a more efficient implementation. Accordingly the circuit is checked for existence of multiplexing functions, and merging, when possible, of such multiplexing functions to achieve the ability to instantiate the multiplexing functionality with a large multiplexer.
摘要翻译：在设计集成电路（IC）的过程中，通常情况下功能描述被转换为多路复用器。在一些情况下，将两个或多个多路复用器组合成较大的多路复用器以识别原始寄存器传送级（RTL）中的潜在设计问题将是更有效的。这种早期检测可以防止路由拥塞问题，这将在以后修复太昂贵。大多路复用器被定义为具有高于预定阈值的多个输入和控制信号的多路复用器。当检测到这样的多路复用功能时，功能可以在电路中用具有更高效实施的大型多路复用器代替。因此，检查电路是否存在多路复用功能，并且在可能的情况下合并这些复用功能以实现利用大多路复用器来实现多路复用功能的能力。

8. 发明授权

US08984469B2 System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption 有权
标题翻译：用于加强电路元件以减少集成电路的功耗的系统和方法
公开(公告)号：US08984469B2
公开(公告)日：2015-03-17
申请号：US14106374
申请日：2013-12-13
申请人： Atrenta, Inc.
发明人： Solaiman Rahim , Mohammad H. Movahed-Ezazi , Siddharth Guha , Vaibhav Jain
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/50 , G06F17/505 , G06F2217/78
摘要： A system and method enable strengthening of flip-Flops (FFs) in an integrated circuit (IC) for the purpose of reducing power consumption. This is achieved by using stability condition (STC) and observability don't-care (ODC) techniques. Strengthening enable is defined as ensuring that a FF later in the fan-out is enabled only when a FF earlier in the fan-out is driving a signal to that later FF. In an embodiment the fan-in of a FF is traversed and the STC or ODC is determined for the FF. Dependent on the determination a STC controller or an ODC controller is added to control the FF's enable signal. In an embodiment the power savings is checked and a controller is added only if there is a reduction in overall power consumption resulting from the addition of the controller.
摘要翻译：为了降低功耗，系统和方法能够强化集成电路（IC）中的触发器（FF）。这通过使用稳定性条件（STC）和可观察性（ODC）技术来实现。加强使能被定义为确保仅当FF中较早的FF正在向稍后的FF驱动信号时才能启用扇出的FF。在一个实施例中，FF的扇入遍历，并且为FF确定STC或ODC。根据确定添加STC控制器或ODC控制器来控制FF的使能信号。在一个实施例中，检查功率节省，并且仅当由于添加控制器而导致的总功耗的降低时才添加控制器。

9. 发明申请

US20140282347A1 SYSTEM AND METHOD FOR STRENGTHENING OF A CIRCUIT ELEMENT TO REDUCE AN INTEGRATED CIRCUIT'S POWER CONSUMPTION 有权
标题翻译：用于加强电路元件以减少集成电路的功耗的系统和方法
公开(公告)号：US20140282347A1
公开(公告)日：2014-09-18
申请号：US14106374
申请日：2013-12-13
申请人： Atrenta, Inc.
发明人： Solaiman Rahim , Mohammad H. Movahed-Ezazi , Siddharth Guha , Vaibhav Jain
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/505 , G06F2217/78
摘要： A system and method enable strengthening of flip-Flops (FFs) in an integrated circuit (IC) for the purpose of reducing power consumption. This is achieved by using stability condition (STC) and observability don't-care (ODC) techniques. Strengthening enable is defined as ensuring that a FF later in the fan-out is enabled only when a FF earlier in the fan-out is driving a signal to that later FF. In an embodiment the fan-in of a FF is traversed and the STC or ODC is determined for the FF. Dependent on the determination a STC controller or an ODC controller is added to control the FF's enable signal. In an embodiment the power savings is checked and a controller is added only if there is a reduction in overall power consumption resulting from the addition of the controller.
摘要翻译：为了降低功耗，系统和方法能够强化集成电路（IC）中的触发器（FF）。这通过使用稳定性条件（STC）和可观察性（ODC）技术来实现。加强使能被定义为确保仅当FF中较早的FF正在向稍后的FF驱动信号时才能启用扇出的FF。在一个实施例中，FF的扇入遍历，并且为FF确定STC或ODC。根据确定添加STC控制器或ODC控制器来控制FF的使能信号。在一个实施例中，检查功率节省，并且仅当由于添加控制器而导致的总功耗的降低时才添加控制器。

10. 发明授权

US08656326B1 Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design 有权
标题翻译：使用网络活动和XOR技术的半导体设计的连续时钟门控，包括已经选通的管道设计
公开(公告)号：US08656326B1
公开(公告)日：2014-02-18
申请号：US13766017
申请日：2013-02-13
申请人： Atrenta, Inc.
发明人： Solaiman Rahim , Mohammad H. Movahed-Ezazi
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505 , G06F17/5045
摘要： The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.
摘要翻译：电路设计过程需要减少大型集成电路和片上系统设计的功耗的方法。这通常通过引入时钟门控的过程来实现，从而启用或禁用与电路内的特定功能块相关联的触发器。然而，电路中的这种变化需要综合和验证，以确保设计和操作的正确性，因为顺序时钟选通动态地改变状态功能。因此，有必要定义适应于设计中这种动态变化的合成方法。根据实施例，顺序时钟门控方法使用异或技术来克服现有技术方法的缺陷。

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