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1. 发明授权

US09083524B2 Systems and methods for sending an acknowledgement message in a wireless communication system 有权
标题翻译：用于在无线通信系统中发送确认消息的系统和方法
公开(公告)号：US09083524B2
公开(公告)日：2015-07-14
申请号：US12409832
申请日：2009-03-24
申请人： Arunava Chaudhuri , Hemanth Sampath , Raghu N. Challa , Ravi Palanki , Sunil K. Kandukuri Narayan
发明人： Arunava Chaudhuri , Hemanth Sampath , Raghu N. Challa , Ravi Palanki , Sunil K. Kandukuri Narayan
IPC分类号： H04L1/20 , H04L1/16
CPC分类号： H04L1/20 , H04L1/1607 , H04L1/208
摘要： A method for sending an acknowledgment message in a wireless communication system is disclosed. A first signal is received before receiving a second signal from a transmitter. Decoded first data is extracted from the first signal. A third signal is produced by encoding and modulating the decoded first data. The second signal is demodulated to produce second symbols. The third signal and the second symbols are correlated.
摘要翻译：公开了一种用于在无线通信系统中发送确认消息的方法。在从发射机接收第二信号之前接收第一信号。从第一信号中提取解码的第一数据。通过对解码的第一数据进行编码和调制来产生第三信号。第二信号被解调以产生第二符号。第三信号和第二符号相关。

2. 发明申请

US20090245436A1 Systems and Methods For Sending An Acknowledgement Message In A Wireless Communication System 有权
标题翻译：用于在无线通信系统中发送确认消息的系统和方法
公开(公告)号：US20090245436A1
公开(公告)日：2009-10-01
申请号：US12409832
申请日：2009-03-24
申请人： Arunava Chaudhuri , Hemanth Sampath , Raghu N. Challa , Ravi Palanki , Sunil K. Kandukuri narayana
发明人： Arunava Chaudhuri , Hemanth Sampath , Raghu N. Challa , Ravi Palanki , Sunil K. Kandukuri narayana
IPC分类号： H04L27/06
CPC分类号： H04L1/20 , H04L1/1607 , H04L1/208
摘要： A method for sending an acknowledgment message in a wireless communication system is disclosed. A first signal is received before receiving a second signal from a transmitter. Decoded first data is extracted from the first signal. A third signal is produced by encoding and modulating the decoded first data. The second signal is demodulated to produce second symbols. The third signal and the second symbols are correlated.
摘要翻译：公开了一种用于在无线通信系统中发送确认消息的方法。在从发射机接收第二信号之前接收第一信号。从第一信号中提取解码的第一数据。通过对解码的第一数据进行编码和调制来产生第三信号。第二信号被解调以产生第二符号。第三信号和第二符号相关。

3. 发明申请

US20090248774A1 REUSE ENGINE WITH TASK LIST FOR FAST FOURIER TRANSFORM AND METHOD OF USING THE SAME 有权
标题翻译：用快速傅里叶变换的任务列表重新使用发动机及其使用方法
公开(公告)号：US20090248774A1
公开(公告)日：2009-10-01
申请号：US12411728
申请日：2009-03-26
申请人： Arunava Chaudhuri , Hemanth Sampath , Iwen Yao , Jeremy H. Lin , Raghu N. Challa , Min Wu
发明人： Arunava Chaudhuri , Hemanth Sampath , Iwen Yao , Jeremy H. Lin , Raghu N. Challa , Min Wu
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , H04L5/0007 , H04L5/0023 , H04L5/0053 , H04L27/265 , H04L27/2662
摘要： An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.
摘要翻译：用于执行傅里叶变换的改进的处理引擎包括配置成处理顺序指令软件命令的指令处理器和耦合到指令处理器的傅里叶变换引擎。傅立叶变换引擎被配置为对串行数据流执行傅里叶变换。傅里叶变换引擎被配置为经由一组软件任务从指令处理器接收配置信息和操作数据。

4. 发明授权

US08738680B2 Reuse engine with task list for fast fourier transform and method of using the same 有权
标题翻译：使用任务列表重新使用引擎进行快速傅立叶变换和使用相同的方法
公开(公告)号：US08738680B2
公开(公告)日：2014-05-27
申请号：US12411728
申请日：2009-03-26
申请人： Arunava Chaudhuri , Hemanth Sampath , Iwen Yao , Jeremy H. Lin , Raghu N. Challa , Min Wu
发明人： Arunava Chaudhuri , Hemanth Sampath , Iwen Yao , Jeremy H. Lin , Raghu N. Challa , Min Wu
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , H04L5/0007 , H04L5/0023 , H04L5/0053 , H04L27/265 , H04L27/2662
摘要： An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.
摘要翻译：用于执行傅里叶变换的改进的处理引擎包括配置成处理顺序指令软件命令的指令处理器和耦合到指令处理器的傅里叶变换引擎。傅立叶变换引擎被配置为对串行数据流执行傅里叶变换。傅里叶变换引擎被配置为经由一组软件任务从指令处理器接收配置信息和操作数据。

5. 发明授权

US08520500B2 Buffered demod and demap functions 失效
标题翻译：缓冲解调和解映射功能
公开(公告)号：US08520500B2
公开(公告)日：2013-08-27
申请号：US12407482
申请日：2009-03-19
申请人： Jeremy H. Lin , Arunava Chaudhuri , Raghu N. Challa , Hemanth Sampath
发明人： Jeremy H. Lin , Arunava Chaudhuri , Raghu N. Challa , Hemanth Sampath
IPC分类号： H04J11/00
CPC分类号： H04L25/0202 , H04L5/0007 , H04L5/0023 , H04L27/265
摘要： An apparatus operable in a wireless communication system, the apparatus may include an FFT symbol buffer and a demapping device. The FFT symbol buffer can feed FFT symbol data derived from received communication signals to a channel estimation device and a shared buffer. The channel estimation device can also provide intermediate data to the shared buffer. The intermediate data may be in tile form and can be derived from the FFT symbol data. Further, the intermediate data can be stored in the shared buffer. The demapping device can extract the intermediate data from the shared buffer in various forms including sub-packet form.
摘要翻译：一种在无线通信系统中可操作的装置，该装置可以包括FFT符号缓冲器和解映射装置。 FFT符号缓冲器可以将从接收到的通信信号导出的FFT符号数据馈送到信道估计装置和共享缓冲器。信道估计装置还可以向共享缓冲器提供中间数据。中间数据可以是瓦片形式，并且可以从FFT符号数据导出。此外，中间数据可以存储在共享缓冲器中。解映射设备可以以包括子包形式的各种形式从共享缓冲器提取中间数据。

6. 发明申请

US20090245091A1 BUFFERED DEMOD AND DEMAP FUNCTIONS 失效
标题翻译：缓冲的演示和演示功能
公开(公告)号：US20090245091A1
公开(公告)日：2009-10-01
申请号：US12407482
申请日：2009-03-19
申请人： Jeremy H. Lin , Arunava Chaudhuri , Raghu N. Challa , Hemanth Sampath
发明人： Jeremy H. Lin , Arunava Chaudhuri , Raghu N. Challa , Hemanth Sampath
IPC分类号： H04J11/00
CPC分类号： H04L25/0202 , H04L5/0007 , H04L5/0023 , H04L27/265
摘要： An apparatus operable in a wireless communication system, the apparatus may include an FFT symbol buffer and a demapping device. The FFT symbol buffer can feed FFT symbol data derived from received communication signals to a channel estimation device and a shared buffer. The channel estimation device can also provide intermediate data to the shared buffer. The intermediate data may be in tile form and can be derived from the FFT symbol data. Further, the intermediate data can be stored in the shared buffer. The demapping device can extract the intermediate data from the shared buffer in various forms including sub-packet form.
摘要翻译：一种在无线通信系统中可操作的装置，该装置可以包括FFT符号缓冲器和解映射装置。 FFT符号缓冲器可以将从接收到的通信信号导出的FFT符号数据馈送到信道估计装置和共享缓冲器。信道估计装置还可以向共享缓冲器提供中间数据。中间数据可以是瓦片形式，并且可以从FFT符号数据导出。此外，中间数据可以存储在共享缓冲器中。解映射设备可以以包括子包形式的各种形式从共享缓冲器提取中间数据。

7. 发明授权

US08699529B2 Broadband pilot channel estimation using a reduced order FFT and a hardware interpolator 有权
标题翻译：使用降阶FFT和硬件内插器的宽带导频信道估计
公开(公告)号：US08699529B2
公开(公告)日：2014-04-15
申请号：US12405082
申请日：2009-03-16
申请人： Petru Cristian Budianu , Arunava Chaudhuri , Raghu N. Challa
发明人： Petru Cristian Budianu , Arunava Chaudhuri , Raghu N. Challa
IPC分类号： H04J1/02 , H04L25/02 , H04J11/00
CPC分类号： H04L25/0202 , H04B1/76 , H04J11/00 , H04L25/0212 , H04L25/023 , H04L25/0232
摘要： Within a receiver, a channel estimation mechanism involves a hardware interpolator. In a first mode, narrowband pilot values are analyzed to generate channel parameters that are supplied to the interpolator such that the interpolator generates channel estimate values. The channel estimate values are used to demodulate a tile of a frame. In a second mode, broadband pilot values are supplied to an IFFT, thereby generating time domain values. After time domain processing, an FFT is employed to generate intermediate channel estimate values. These intermediate values are analyzed to determine channel parameters, which in turn are supplied to the hardware interpolator so that the interpolator generates a larger number of channel estimate values. After phase adjustment, the channel estimate values are used in demodulation. Use of the interpolator in the broadband mode allows the FFT employed to be of a smaller order, and to consume less power and/or processing resources.
摘要翻译：在接收机内，信道估计机制涉及硬件插值器。在第一模式中，分析窄带导频值以产生提供给内插器的信道参数，使得内插器生成信道估计值。信道估计值用于解调帧的瓦片。在第二模式中，宽带导频值被提供给IFFT，从而产生时域值。在时域处理之后，采用FFT来产生中间信道估计值。分析这些中间值以确定信道参数，其又被提供给硬件插值器，使得内插器产生更大数量的信道估计值。相位调整后，信道估计值用于解调。在宽带模式下使用内插器允许所采用的FFT具有较小的次序，并且消耗更少的功率和/或处理资源。

8. 发明申请

US20090245090A1 Broadband Pilot Channel Estimation Using A Reduced Order FFT and a Hardware Interpolator 有权
标题翻译：使用降序FFT和硬件插值器的宽带导频信道估计
公开(公告)号：US20090245090A1
公开(公告)日：2009-10-01
申请号：US12405082
申请日：2009-03-16
申请人： Petru Cristian Budianu , Arunava Chaudhuri , Raghu N. Challa
发明人： Petru Cristian Budianu , Arunava Chaudhuri , Raghu N. Challa
IPC分类号： H04J11/00 , H04K1/10
CPC分类号： H04L25/0202 , H04B1/76 , H04J11/00 , H04L25/0212 , H04L25/023 , H04L25/0232
摘要： Within a receiver, a channel estimation mechanism involves a hardware interpolator. In a first mode, narrowband pilot values are analyzed to generate channel parameters that are supplied to the interpolator such that the interpolator generates channel estimate values. The channel estimate values are used to demodulate a tile of a frame. In a second mode, broadband pilot values are supplied to an IFFT, thereby generating time domain values. After time domain processing, an FFT is employed to generate intermediate channel estimate values. These intermediate values are analyzed to determine channel parameters, which in turn are supplied to the hardware interpolator so that the interpolator generates a larger number of channel estimate values. After phase adjustment, the channel estimate values are used in demodulation. Use of the interpolator in the broadband mode allows the FFT employed to be of a smaller order, and to consume less power and/or processing resources.
摘要翻译：在接收机内，信道估计机制涉及硬件插值器。在第一模式中，分析窄带导频值以产生提供给内插器的信道参数，使得内插器生成信道估计值。信道估计值用于解调帧的瓦片。在第二模式中，宽带导频值被提供给IFFT，从而产生时域值。在时域处理之后，采用FFT来产生中间信道估计值。分析这些中间值以确定信道参数，其又被提供给硬件插值器，使得内插器产生更大数量的信道估计值。相位调整后，信道估计值用于解调。在宽带模式下使用内插器允许所采用的FFT具有较小的次序，并且消耗更少的功率和/或处理资源。

9. 发明授权

US08520571B2 Reconfigurable wireless modem sub-circuits to implement multiple air interface standards 有权
标题翻译：可重配置的无线调制解调器子电路实现多个空中接口标准
公开(公告)号：US08520571B2
公开(公告)日：2013-08-27
申请号：US12396270
申请日：2009-03-02
申请人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Ali RostamPisheh , Raghu Challa , Hemanth Sampath , Megan Wu , Joseph Zanotelli , Mrinal Nath
发明人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Ali RostamPisheh , Raghu Challa , Hemanth Sampath , Megan Wu , Joseph Zanotelli , Mrinal Nath
IPC分类号： H04B7/00
CPC分类号： G06F15/7842
摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

10. 发明授权

US08458380B2 Off-line task list architecture utilizing tightly coupled memory system 有权
标题翻译：使用紧密耦合的存储器系统的离线任务列表架构
公开(公告)号：US08458380B2
公开(公告)日：2013-06-04
申请号：US12396217
申请日：2009-03-02
申请人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski , Kevin W. Yen
发明人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski , Kevin W. Yen
IPC分类号： G06F3/00 , G06F9/46
CPC分类号： G06F9/3879 , G06F15/7814
摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

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