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1. 发明授权

US06891396B1 Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks 有权
标题翻译：可重复块在具有分段轨道的现场可编程门阵列中产生非均匀路由架构
公开(公告)号：US06891396B1
公开(公告)日：2005-05-10
申请号：US10330672
申请日：2002-12-27
申请人： Arunangshu Kundu , Eric Sather , William C. Plants
发明人： Arunangshu Kundu , Eric Sather , William C. Plants
IPC分类号： H01L25/00 , H01L27/118 , H03K19/177
CPC分类号： H03K19/17736 , H01L27/118
摘要： The apparatus comprises a repeatable non-uniform segmented routing architecture in a field programmable gate array having a plurality of sets of routing tracks having a first and last track position proceeding in a first direction and having at least one programmable element and at least one direct address device. The tracks are partitioned into uniform lengths and a track in the last position crosses over to a track in the first position immediately prior to said partition. The apparatus of the present system also has a plurality of sets of routing tracks having a first and last track position proceeding in a second direction. The tracks proceeding in the second direction have at least one programmable element and direct address device, wherein the tracks are partitioned into uniform lengths and said last track position crosses over to a first track position immediately prior to said partition.
摘要翻译：该装置包括现场可编程门阵列中的可重复的非均匀分段路由架构，其具有多组路由轨道，其具有在第一方向上进行的第一和最后轨道位置，并且具有至少一个可编程元件和至少一个直接地址设备。轨道被划分成均匀的长度，并且最后位置的轨道在紧接在所述分区之前的第一位置中越过轨道。本系统的装置还具有多组路由轨道，其具有在第二方向上进行的第一和最后轨道位置。在第二方向上进行的轨道具有至少一个可编程元件和直接地址设备，其中轨道被划分成均匀的长度，并且所述最后轨道位置在紧接在所述分区之前跨越到第一轨道位置。

2. 发明授权

US07579869B2 Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks 有权
标题翻译：可重复块在具有分段轨道的现场可编程门阵列中产生非均匀路由架构
公开(公告)号：US07579869B2
公开(公告)日：2009-08-25
申请号：US12131258
申请日：2008-06-02
申请人： Arunangshu Kundu , Eric Sather , William C. Plants
发明人： Arunangshu Kundu , Eric Sather , William C. Plants
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , G11C5/063 , H01L27/118
摘要： A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising: a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks, each set having a first routing track in a first track position, a second routing track in a last track position, a programmable element, and a direct address device for programming the programmable element; wherein at least one of the routing tracks is segmented into non-uniform lengths by the programmable element and the second routing track crosses-over to the first track position in a region adjacent to an edge of the repeatable block; and wherein a first plurality of the routing track sets proceed in a horizontal direction and a second plurality of the routing track sets proceed in a vertical direction.
摘要翻译：在现场可编程门阵列中的可重复的非均匀分段路由架构，包括：可重复的路由轨道块，所述路由轨迹被分组为路由轨道集合，每个路由集合具有处于第一轨道位置的第一路由轨道，第二路由轨迹在最后轨道位置，可编程元件和用于对可编程元件进行编程的直接地址设备; 其中所述路由轨道中的至少一个由所述可编程元件分段成非均匀长度，并且所述第二路由轨道在与所述可重复块的边缘相邻的区域中跨越到所述第一轨道位置; 并且其中第一多个所述路线轨迹组在水平方向上行进，并且所述第二多个所述路线轨迹组在垂直方向上进行。

3. 发明授权

US07075334B1 Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks 失效
标题翻译：可重复块在具有分段轨道的现场可编程门阵列中产生非均匀路由架构
公开(公告)号：US07075334B1
公开(公告)日：2006-07-11
申请号：US11120509
申请日：2005-05-02
申请人： Arunangshu Kundu , Eric Sather , William C. Plants
发明人： Arunangshu Kundu , Eric Sather , William C. Plants
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H01L27/118
摘要： The apparatus comprises a repeatable non-uniform segmented routing architecture in a field programmable gate array having a plurality of sets of routing tracks having a first and last track position proceeding in a first direction and having at least one programmable element and at least one direct address device. The tracks are partitioned into uniform lengths and a track in the last position crosses over to a track in the first position immediately prior to said partition. The apparatus of the present system also has a plurality of sets of routing tracks having a first and last track position proceeding in a second direction. The tracks proceeding in the second direction have at least one programmable element and direct address device, wherein the tracks are partitioned into uniform lengths and said last track position crosses over to a first track position immediately prior to said partition.
摘要翻译：该装置包括现场可编程门阵列中的可重复的非均匀分段路由架构，其具有多组路由轨道，其具有在第一方向上进行的第一和最后轨道位置，并且具有至少一个可编程元件和至少一个直接地址设备。轨道被划分成均匀的长度，并且最后位置的轨道在紧接在所述分区之前的第一位置中越过轨道。本系统的装置还具有多组路由轨道，其具有在第二方向上进行的第一和最后轨道位置。在第二方向上进行的轨道具有至少一个可编程元件和直接地址设备，其中轨道被划分成均匀的长度，并且所述最后轨道位置在紧接在所述分区之前跨越到第一轨道位置。

4. 发明申请

US20080246510A1 REPEATABLE BLOCK PRODUCING A NON-UNIFORM ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY HAVING SEGMENTED TRACKS 有权
标题翻译：在具有划分的轨迹的现场可编程门阵列中生成非均匀路由架构的可重复块
公开(公告)号：US20080246510A1
公开(公告)日：2008-10-09
申请号：US12131258
申请日：2008-06-02
申请人： Arunangshu Kundu , Eric Sather , William C. Plants
发明人： Arunangshu Kundu , Eric Sather , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , G11C5/063 , H01L27/118
摘要： A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising: a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks, each set having a first routing track in a first track position, a second routing track in a last track position, a programmable element, and a direct address device for programming the programmable element; wherein at least one of the routing tracks is segmented into non-uniform lengths by the programmable element and the second routing track crosses-over to the first track position in a region adjacent to an edge of the repeatable block; and wherein a first plurality of the routing track sets proceed in a horizontal direction and a second plurality of the routing track sets proceed in a vertical direction.
摘要翻译：在现场可编程门阵列中的可重复的非均匀分段路由架构，包括：可重复的路由轨道块，所述路由轨迹被分组为路由轨道集合，每个路由集合具有处于第一轨道位置的第一路由轨道，第二路由轨迹在最后轨道位置，可编程元件和用于对可编程元件进行编程的直接地址设备; 其中所述路由轨道中的至少一个由所述可编程元件分段成非均匀长度，并且所述第二路由轨道在与所述可重复块的边缘相邻的区域中跨越到所述第一轨道位置; 并且其中第一多个所述路线轨迹组在水平方向上行进，并且所述第二多个所述路线轨迹组在垂直方向上进行。

5. 发明授权

US07385420B1 Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks 有权
标题翻译：可重复块在具有分段轨道的现场可编程门阵列中产生非均匀路由架构
公开(公告)号：US07385420B1
公开(公告)日：2008-06-10
申请号：US11426541
申请日：2006-06-26
申请人： Arunangshu Kundu , Eric Sather , William C. Plants
发明人： Arunangshu Kundu , Eric Sather , William C. Plants
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , G11C5/063 , H01L27/118
摘要： A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising: a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks, each set having a first routing track in a first track position, a second routing track in a last track position, a programmable element, and a direct address device for programming the programmable element; wherein at least one of the routing tracks is segmented into non-uniform lengths by the programmable element and the second routing track crosses-over to the first track position in a region adjacent to an edge of the repeatable block; and wherein a first plurality of the routing track sets proceed in a horizontal direction and a second plurality of the routing track sets proceed in a vertical direction.
摘要翻译：在现场可编程门阵列中的可重复的非均匀分段路由架构，包括：可重复的路由轨道块，所述路由轨迹被分组为路由轨道集合，每个路由集合具有处于第一轨道位置的第一路由轨道，第二路由轨迹在最后轨道位置，可编程元件和用于对可编程元件进行编程的直接地址设备; 其中所述路由轨道中的至少一个由所述可编程元件分段成非均匀长度，并且所述第二路由轨道在与所述可重复块的边缘相邻的区域中跨越到所述第一轨道位置; 并且其中第一多个所述路线轨迹组在水平方向上行进，并且所述第二多个所述路线轨迹组在垂直方向上进行。

6. 发明授权

US07516303B2 Field programmable gate array and microcontroller system-on-a-chip 有权
标题翻译：现场可编程门阵列和微控制器片上系统
公开(公告)号：US07516303B2
公开(公告)日：2009-04-07
申请号：US11187068
申请日：2005-07-22
申请人： Arunangshu Kundu , Arnold Goldfein , William C. Plants , David Hightower
发明人： Arunangshu Kundu , Arnold Goldfein , William C. Plants , David Hightower
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/7842 , G06F15/7867
摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.
摘要翻译：片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。

7. 发明授权

US07432733B1 Multi-level routing architecture in a field programmable gate array having transmitters and receivers 有权
标题翻译：具有发射机和接收机的现场可编程门阵列中的多级路由架构
公开(公告)号：US07432733B1
公开(公告)日：2008-10-07
申请号：US11531375
申请日：2006-09-13
申请人： Arunangshu Kundu , Venkatesh Narayanan , John McCollum , William C. Plants
发明人： Arunangshu Kundu , Venkatesh Narayanan , John McCollum , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17736
摘要： A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.
摘要翻译：具有多个逻辑集群的现场可编程门阵列（FPGA）中的路由架构，其中每个逻辑集群具有至少两个子集群。逻辑簇以行和列排列，并且每个逻辑簇具有多个接收器组件，多个发射器组件，至少一个缓冲器模块，至少一个顺序逻辑组件和至少一个组合逻辑组件。第一级路由架构可编程地耦合到逻辑集群，并且第二级路由架构可编程地耦合到逻辑集群，并通过至少一个发送器部件和至少一个接收器耦合到第一级路由架构组件。

8. 发明授权

US07385419B1 Dedicated input/output first in/first out module for a field programmable gate array 失效
标题翻译：用于现场可编程门阵列的专用输入/输出先进先出模块
公开(公告)号：US07385419B1
公开(公告)日：2008-06-10
申请号：US11677432
申请日：2007-02-21
申请人： William C. Plants , Arunangshu Kundu
发明人： William C. Plants , Arunangshu Kundu
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1776 , H03K19/17744
摘要： A field programmable gate array architecture having a plurality of input/output pads. The architecture comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; an input/output block controller programmably coupled to the plurality of dedicated input/output first-in/first-out memory blocks; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.
摘要翻译：具有多个输入/输出焊盘的现场可编程门阵列架构。该架构包括：多个逻辑簇; 多个输入/输出群集; 多个输入/输出缓冲器; 多个专用输入/输出先进先出存储块，专用输入/输出先进先出存储块具有耦合到多个输入/输出存储器中的一个的先进先出存储器，输出垫; 可编程地耦合到所述多个专用输入/输出先入/先出存储块的输入/输出块控制器; 以及可编程地耦合逻辑簇，输入/输出缓冲器和输入/输出群集的路由互连架构，其中专用输入/输出先入先出存储器块可编程地耦合在输入/输出缓冲器和输入/ 输出集群。

9. 发明申请

US20090106531A1 FIELD PROGRAMMABLE GATE ARRAY AND MICROCONTROLLER SYSTEM-ON-A-CHIP 有权
标题翻译：现场可编程阵列阵列和微控制器系统
公开(公告)号：US20090106531A1
公开(公告)日：2009-04-23
申请号：US12345409
申请日：2008-12-29
申请人： Arunangshu Kundu , Arnold Goldfein , William C. Plants , David Hightower
发明人： Arunangshu Kundu , Arnold Goldfein , William C. Plants , David Hightower
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F15/7842 , G06F15/7867
摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.
摘要翻译：片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。

10. 发明申请

US20080231319A1 DEDICATED INPUT/OUTPUT FIRST IN/FIRST OUT MODULE FOR A FIELD PROGRAMMABLE GATE ARRAY 审中-公开
标题翻译：用于现场可编程门阵列的专用输入/输出第一个/第一个输出模块
公开(公告)号：US20080231319A1
公开(公告)日：2008-09-25
申请号：US12131722
申请日：2008-06-02
申请人： William C. Plants , Arunangshu Kundu
发明人： William C. Plants , Arunangshu Kundu
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17744
摘要： A field programmable gate array architecture having a plurality of input/output pads. The architecture comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; an input/output block controller programmably coupled to the plurality of dedicated input/output first-in/first-out memory blocks; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.
摘要翻译：具有多个输入/输出焊盘的现场可编程门阵列架构。该架构包括：多个逻辑簇; 多个输入/输出群集; 多个输入/输出缓冲器; 多个专用输入/输出先进先出存储块，专用输入/输出先进先出存储块具有耦合到多个输入/输出存储器中的一个的先进先出存储器，输出垫; 可编程地耦合到所述多个专用输入/输出先入/先出存储块的输入/输出块控制器; 以及可编程地耦合逻辑簇，输入/输出缓冲器和输入/输出群集的路由互连结构，其中专用输入/输出先入先出存储块可编程地耦合在输入/输出缓冲器与输入/ 输出集群。

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