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1. 发明授权

US07626828B1 Providing a resistive element between reference plane layers in a circuit board 有权
标题翻译：在电路板中的参考平面层之间提供电阻元件
公开(公告)号：US07626828B1
公开(公告)日：2009-12-01
申请号：US10630886
申请日：2003-07-30
申请人： Arthur R. Alexander , Jun Fan , James L. Knighten , Norman W. Smith
发明人： Arthur R. Alexander , Jun Fan , James L. Knighten , Norman W. Smith
IPC分类号： H05K1/18
CPC分类号： H05K1/0234 , H05K1/0231 , H05K1/167 , H05K1/185 , H05K2201/09309 , H05K2201/10022 , H05K2201/1053
摘要： A circuit board includes reference plane layers and a dielectric between the reference plane layers. A resistive element is also provided between the reference plane layers to provide a resistive path between the reference plane layers. Optimally, a decoupling capacitor is provided having a first electrode electrically connected to the resistive element, and a second electrode electrically connected to one of the reference plane layers.
摘要翻译：电路板包括参考平面层和参考平面层之间的电介质。在参考平面层之间还提供电阻元件以提供参考平面层之间的电阻路径。最佳地，提供了具有电连接到电阻元件的第一电极和电连接到参考平面层之一的第二电极的去耦电容器。

2. 发明授权

US07271348B1 Providing decoupling capacitors in a circuit board 有权
标题翻译：在电路板中提供去耦电容
公开(公告)号：US07271348B1
公开(公告)日：2007-09-18
申请号：US10670829
申请日：2003-09-25
申请人： Jun Fan , Arthur R. Alexander , Norman W. Smith , James L. Knighten
发明人： Jun Fan , Arthur R. Alexander , Norman W. Smith , James L. Knighten
IPC分类号： H05K1/16
CPC分类号： H05K1/0231 , H05K1/185 , H05K3/4611 , H05K2201/09309 , H05K2201/10636 , Y02P70/611 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165
摘要： A circuit board includes first and second reference plane layers. A first decoupling capacitor is mounted to a surface of the first reference plane layer, and a second decoupling capacitor is mounted to a surface of the second reference plane layer. Vias extend generally along a first direction through the circuit board. The first and second decoupling capacitors are aligned generally along the first direction to increase an amount of space through which the vias are extendable.
摘要翻译：电路板包括第一和第二参考平面层。第一去耦电容器安装到第一参考平面层的表面，并且第二去耦电容器被安装到第二参考平面层的表面。通孔沿着第一方向大致延伸穿过电路板。第一和第二去耦电容器大致沿着第一方向排列，以增加通孔可扩展的空间量。

3. 发明授权

US06887105B2 Providing shields to reduce electromagnetic interference from connectors 失效
标题翻译：提供屏蔽以减少连接器的电磁干扰
公开(公告)号：US06887105B2
公开(公告)日：2005-05-03
申请号：US09881464
申请日：2001-06-14
申请人： James L. Knighten , Arthur R. Alexander
发明人： James L. Knighten , Arthur R. Alexander
IPC分类号： H01R13/648 , H01R13/52 , H01R13/6473 , H01R13/6592 , H01R13/6596 , H01R13/73 , H01R13/74 , H01R9/03
CPC分类号： H01R13/6473 , H01R13/5213 , H01R13/6592 , H01R13/6596 , H01R13/746 , Y10S439/939
摘要： A method and apparatus to provide a shield assembly for a connector, with the shield assembly having a cover to enclose the connector and a neck portion adapted to surround an outer surface of a portion of the cable. An inner surface of the neck portion makes contact with the outer surface of the cable. When the cable carries a high frequency signal, a capacitive impedance is provided between the neck portion and an outer shield of the cable to reduce electromagnetic signal leakage. Alternatively, the neck portion can make electrical contact with the cable shield, either by use of elements protruding from the inner surface of the neck portion or by removing an insulating jacket of the cable.
摘要翻译：一种提供用于连接器的屏蔽组件的方法和装置，其中屏蔽组件具有盖以封闭连接器，以及适于围绕电缆的一部分的外表面的颈部。颈部的内表面与电缆的外表面接触。当电缆承载高频信号时，在电缆的颈部和外屏蔽之间提供电容性阻抗以减少电磁信号泄漏。或者，颈部可以通过使用从颈部的内表面突出的元件或通过去除电缆的绝缘护套而与电缆屏蔽件电接触。

4. 发明授权

US5586011A Side plated electromagnetic interference shield strip for a printed circuit board 失效
标题翻译：用于印刷电路板的侧面电磁干扰屏蔽条
公开(公告)号：US5586011A
公开(公告)日：1996-12-17
申请号：US297346
申请日：1994-08-29
申请人： Arthur R. Alexander
发明人： Arthur R. Alexander
IPC分类号： H05K1/00 , H05K1/02 , H05K9/00
CPC分类号： H05K9/0039 , H05K1/0218 , H05K1/0298
摘要： An electric circuit board including EMI shielding. The board comprises a substrate including top and bottom surfaces and at least one internal ground layer, the internal ground layer being electrically insulated from the external surfaces of the substrate. A plurality of vias are formed in the substrate near the edges of the substrate, each via providing an opening from the surface of the substrate to the internal ground layer A metal plating is applied to the vias, the edges of the substrate and the perimeter of the surface of the substrate, the metal plating along the substrate perimeter being applied over the plated-up vias to electrically connect the ground plane with the metal plating applied to the edges of the substrate.
摘要翻译：包括EMI屏蔽的电路板。该基板包括一个包括顶面和底面以及至少一个内部接地层的基板，该内部接地层与该基板的外表面电绝缘。在基板的靠近基板的边缘处形成多个通孔，每个通孔提供从基板的表面到内部接地层A的开口。金属镀层被施加到通孔，基板的边缘和周边衬底的表面，沿着衬底周边的金属电镀施加在电镀通孔上，以将接地平面与施加到衬底的边缘的金属电镀电连接。

5. 发明授权

US5495394A Three dimensional die packaging in multi-chip modules 失效
标题翻译：三维模块封装在多芯片模块中
公开(公告)号：US5495394A
公开(公告)日：1996-02-27
申请号：US361062
申请日：1994-12-19
申请人： Bruce E. Kornfeld , Arthur R. Alexander
发明人： Bruce E. Kornfeld , Arthur R. Alexander
IPC分类号： H01L25/065 , H01R4/58 , H05K1/14 , H05K1/11 , H05K1/18
CPC分类号： H01L25/0652 , H01L2924/0002 , H01R4/58
摘要： A multi-chip module wherein electrical components, such as integrated circuit devices, are packaged in a three dimensional arrangement. The multi-chip module includes a first, or upper, substrate including a signal layer formed on the top surface of the substrate and at least one integrated circuit device mounted to the top surface of the substrate and electrically connected to the signal layer. The module further includes a second, or internal, substrate, also including a first signal layer formed on the top surface of the substrate and at least one integrated circuit device mounted to the top surface of the substrate and electrically connected with the signal layer formed on the top surface of the second substrate. The second substrate includes a cavity through the substrate corresponding to each integrated circuit device mounted thereto. Each integrated circuit device mounted to the second substrate is placed within its corresponding cavity so that its top and bottom surfaces are flush with the top and bottom surfaces of the second substrate. Electrical signal paths are provided through the first substrate to electrically connect the integrated circuit devices mounted to the first and second substrates, and through the first and second substrates to electrically connect the multi-chip module components and circuitry to a printed circuit board to which the module is mounted. The multi-chip module may include two, three, or more signal layers and substrates connected as described herein.
摘要翻译：一种多芯片模块，其中诸如集成电路装置的电气部件以三维布置被封装。多芯片模块包括第一或上部基板，其包括形成在基板的顶表面上的信号层和安装到基板的顶表面并电连接到信号层的至少一个集成电路装置。该模块还包括第二或内部衬底，其还包括形成在衬底的顶表面上的第一信号层和安装到衬底顶表面的至少一个集成电路器件，并与形成在衬底上的信号层电连接第二基板的顶表面。第二基板包括与安装在其上的每个集成电路装置对应的通过基板的空腔。安装到第二基板的每个集成电路装置被放置在其对应的空腔内，使得其顶表面和底表面与第二基板的顶表面和底表面齐平。电信号路径被提供穿过第一衬底以电连接安装到第一和第二衬底的集成电路器件，并且通过第一和第二衬底将多芯片模块组件和电路电连接到印刷电路板，模块已安装。多芯片模块可以包括如本文所述连接的两个，三个或更多个信号层和衬底。

6. 发明授权

US07216422B2 Method of forming a capacitor assembly in a circuit board 有权
标题翻译：在电路板中形成电容器组件的方法
公开(公告)号：US07216422B2
公开(公告)日：2007-05-15
申请号：US11007010
申请日：2004-12-08
申请人： Jun Fan , James L. Knighten , Arthur R. Alexander , Norman W. Smith
发明人： Jun Fan , James L. Knighten , Arthur R. Alexander , Norman W. Smith
IPC分类号： H05K3/30
CPC分类号： H05K1/0231 , H05K1/185 , H05K3/4611 , H05K2201/09309 , H05K2201/10636 , Y02P70/611 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165
摘要： A circuit board includes an assembly having first and second power reference plane layers, and an insulator layer between the first and second power reference plane layers. Discrete decoupling capacitors are further provided with the assembly. Additional layers are provided above and below the assembly.
摘要翻译：电路板包括具有第一和第二功率参考平面层的组件，以及在第一和第二功率参考平面层之间的绝缘体层。离散去耦电容器还具有组件。在组件的上方和下方提供附加层。

7. 发明授权

US07196906B1 Circuit board having segments with different signal speed characteristics 有权
标题翻译：具有不同信号速度特性的电路板
公开(公告)号：US07196906B1
公开(公告)日：2007-03-27
申请号：US10641476
申请日：2003-08-15
申请人： Arthur R. Alexander , James L. Knighten , Jun Fan , Norman W. Smith
发明人： Arthur R. Alexander , James L. Knighten , Jun Fan , Norman W. Smith
IPC分类号： H05K7/02
CPC分类号： H05K1/186 , H05K1/024 , H05K3/429 , H05K3/4623 , H05K3/4688 , H05K2201/09536 , H05K2201/09718 , H05K2203/061
摘要： A circuit board includes multiple segments, with a first segment having plural signal layers and a second segment having plural signal layers. Signal paths provided by signal layers of the first segment exhibit higher speed signal transmission capability than signal paths provided by the signal layers of the second segment.
摘要翻译：电路板包括多个段，具有多个信号层的第一段和具有多个信号层的第二段。由第一段的信号层提供的信号路径显示比由第二段的信号层提供的信号路径更高的速度信号传输能力。

8. 发明授权

US07045719B1 Enhancing signal path characteristics in a circuit board 有权
标题翻译：增强电路板中的信号路径特性
公开(公告)号：US07045719B1
公开(公告)日：2006-05-16
申请号：US10274573
申请日：2002-10-21
申请人： Arthur R. Alexander , James L. Knighten , Jun Fan
发明人： Arthur R. Alexander , James L. Knighten , Jun Fan
IPC分类号： H01R12/04
CPC分类号： H05K1/0251 , H05K1/0298 , H05K1/116 , H05K1/185 , H05K3/429 , H05K2201/09327 , H05K2201/09718 , Y10T29/49165
摘要： A circuit board includes multiple signal layers, in which signal lines are routed, and power reference plane layers, in which power reference planes (e.g., power supply voltage or ground) are provided. Vias are passed through at least one signal layer and at least one power reference plane layer, or alternatively, vias are passed through at least two power reference plane layers. In one arrangement, a first clearance is defined around the via at the signal layer and a second clearance is defined around the via at the power reference plane layer. The second clearance is larger in size than the first clearance to match or tailor the impedance of the via as closely as possible with the impedance of the signal line that the via is electrically connected to. In another arrangement, clearances around vias at different power reference plane layers are selected to have different sizes to enhance the ability of one of the power reference plane layers (the one with a smaller clearance size) to carry a higher current level.
摘要翻译：电路板包括其中信号线路由的多个信号层和功率参考平面层，其中提供功率参考平面（例如，电源电压或地）。通孔通过至少一个信号层和至少一个功率参考平面层，或者替代地，通孔穿过至少两个功率参考平面层。在一种布置中，在信号层周围围绕通孔限定第一间隙，并且在功率参考平面层周围的通孔周围限定第二间隙。第二间隙的尺寸大于第一间隙，以便匹配或调整通孔的阻抗尽可能接近通孔电连接到的信号线的阻抗。在另一种布置中，选择不同功率参考平面层上的通孔周围的间隙以具有不同的尺寸以增强功率参考平面层（具有较小的间隙尺寸的一个）之一的能力承载更高的电流水平。

9. 发明授权

US07435912B1 Tailoring via impedance on a circuit board 失效
标题翻译：通过电路板上的阻抗进行裁剪
公开(公告)号：US07435912B1
公开(公告)日：2008-10-14
申请号：US10145436
申请日：2002-05-14
申请人： Arthur R. Alexander , James L. Knighten , Jun Fan
发明人： Arthur R. Alexander , James L. Knighten , Jun Fan
IPC分类号： H01R12/04 , H05K1/11
CPC分类号： H05K1/0251 , H05K1/0298 , H05K1/116 , H05K1/185 , H05K3/429 , H05K2201/09327 , H05K2201/09718 , Y10T29/49165
摘要： A circuit board includes multiple signal layers, in which signal lines are routed, and reference plane layers, in which power reference planes are provided. To connect signal lines at different signal layers, vias are passed through at least one signal layer and at least one reference plane layer. At the one signal layer, a first clearance (or anti-pad) is defined around the via. At the reference plane layer, a second clearance is defined around the via. The second clearance is larger in size than the first clearance to match the impedance of the via as closely as possible with the impedance of a signal line the via is electrically connected to.
摘要翻译：电路板包括信号线路由的多个信号层以及提供功率参考平面的参考平面层。为了在不同的信号层连接信号线，通孔通过至少一个信号层和至少一个参考平面层。在一个信号层处，围绕通孔限定第一间隙（或抗焊盘）。在参考平面层，围绕通孔限定第二间隙。第二间隙的尺寸大于第一间隙，以使通孔的阻抗尽可能接近通孔电连接到的信号线的阻抗。

10. 发明授权

US06844505B1 Reducing noise effects in circuit boards 失效
标题翻译：降低电路板噪声
公开(公告)号：US06844505B1
公开(公告)日：2005-01-18
申请号：US10287116
申请日：2002-11-04
申请人： Jun Fan , James L. Knighten , Arthur R. Alexander , Norman W. Smith
发明人： Jun Fan , James L. Knighten , Arthur R. Alexander , Norman W. Smith
IPC分类号： H05K1/02 , H05K1/18 , H05K3/46 , H05K1/16
CPC分类号： H05K1/0231 , H05K1/185 , H05K3/4611 , H05K2201/09309 , H05K2201/10636 , Y02P70/611 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165
摘要： A circuit board includes an assembly having first and second power reference plane layers, and an insulator layer between the first and second power reference plane layers. Discrete decoupling capacitors are further provided with the assembly. Additional layers are provided above and below the assembly.
摘要翻译：电路板包括具有第一和第二功率参考平面层的组件，以及在第一和第二功率参考平面层之间的绝缘体层。离散去耦电容器还具有组件。在组件的上方和下方提供附加层。

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